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nt7502 65 x 132 ram - m a p lcd controller / driver features direct ram da ta displ a y usin g the disp la y ram. w hen ram data bit is 0, it is n o t dis p la yed. w h en r a m data bit is 1, it is displa ye d. (at normal displa y) ram capacit y: 65 x 132 = 85 8 0 bits man y comm a nd functi ons: read/w r ite di spla y data. displ a y on/ o ff. normal/reverse dis pla y . pag e address set. set displ a y s t art line. set lcd bias, electronic co ntrast contro l s , v0 voltag e reg u lati on intern al resisto r ratio set, read mo dif y w r ite, select segme n t drive r direction, po w e r save high-s p e ed 8- b i t microproc ess o r interfac e a llo w i ng dir e ct conn ection to b o th the 80 80 a nd 68 00 serial interface po w e r su ppl y v o ltag e: 2.4 - 3.5v maximum 12v lcd driv ing o u t put voltage 2x / 3x / 4x on chip dc-dc converter voltag e regu lat o r voltag e follo w e r on-chip osc illa tor gener a l des c ription t he n t 7502 is a single-c h i p l cd driver for d o t-matrix l i qu id cr y s tal d i spl a ys w h ich is directl y c o n nectab l e to a microcomp u ter bus. it accepts 8-bit ser i al or paral lel dis p la y data directl y s ent from a micr ocomput er an d stores it in an on-chi p displ a y ram. it generates a lc d drive signa l inde pe nde nt of the microproc essor clock. t he set of the on-chi p dis p la y ram of 65 x 132 b i ts and a one-to- one cor r espo nde nce b e t w e e n lcd p anel p i xel d o ts and o n -chi p r a m bits permit i m pleme n tatio n of displ a ys w i th a hig h degr ee of freedom. t he n t 7502 contai ns 65 co mmon outp u t circuits an d 13 2 segme n t outpu t circuits, so that a sing le chi p of nt 7502 ca n make 65 x 13 2, 55 x 13 2, 49 x 1 32 an d 33 x 13 2 dot displ a ys w i th p ad opti on (dut y1, dut y0). no e x tern al op eratio n clock i s require d for ram read/ w r it e oper ations. ac cordin gl y, this driver can b e oper ated w i th a minimum cu rrent consu m ption an d its onboa rd lo w - curr ent-co n sumpti on li qu id cr y s t a l po wer supp l y c a n implem ent a high-p e rforma nc e hand y d i spl a y s y st em w i t h minimum curr ent consum ption an d the smallest lsi config uratio n. pin configur ation nt7502h-tabf1 (copper side view) v4 cs 1 cs 2 re s a0 wr rd d0 d1 d2 d3 d4 d5 d6 d7 duty 0 duty 1 vd d v dd2 vss vou t nc c ap3 + c ap1 - c ap2 + c ap2 - vext vr s v1 v2 v3 nc v0 vr m/ s cls c86 p/ s hp m nc nc nc nc fr cl do f nc irs c ap1 + 40 41 42 43 44 45 46 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 47 243 244 245 246 247 co m 6 2 co m 6 3 co m s frs fr 211 212 213 214 215 seg1 3 0 seg1 3 1 co m 3 2 co m 3 3 co m 3 4 78 79 80 81 82 83 co m 1 co m 0 co m s seg0 seg1 seg2 49 50 51 48 co m 3 1 co m 3 0 co m 2 9 co m 2 8 1 v1.0
nt7502 pad con f igu r ation 101 117 118 282 281 298 nt7502 100 1 dummy dummy dummy0 dummy4 dummy5 dummy11 alk_l alk_r 2
nt7502 block diagra m segment driver common driver shift register com s power supply circuit display data latch 132*65-dot display data ram line address decoder i/o buffer circuit line counter initial display line register output status selector circuit column address decoder 8-bit column address counter 8-bit column address counter page address register display timing generator circuit bus holder command decoder bus holder oscillator microprocessor interface i/o buffer seg0 seg131 com0 com63 coms v 0 v2 v4 v1 v3 vss cap1+ cap1- cap2+ cap2- cap3+ v out cls cs2 a0 rd (e) wr ) w / r ( c86 p/s res 1 cs v dd d7 (si) d5 d4 d3 d2 d1 d0 d6 (scl) tmps v dd2 v r v rs irs hpm v ext frs fr cl dof m/s duty0 duty1 3
nt7502 pad des c ription po w e r supply pad no. symbol i/o descriptions 30 - 33 v dd supp l y 2.4 - 3.5v po w e r supp l y inp u t. t hese pads m u st be conn ect ed eac h other 10, 16, 26, 53, 71, 77, 81, 91 v dd supp l y 2.4 - 3.5v po w e r supp l y outp u t for pad opti o n 34 - 36 v dd2 s u p p l y t h is is the reference po w e r s uppl y for t he step-u p voltag e circuit for the lcd. t hese pads must be conn ect ed eac h other 37 - 40 v ss supp l y ground. t hese pads must be conn ected e a c h other 7, 13, 25, 29 , 56, 69 - 70, 74, 79, 83 v ss supp l y ground o u tput for pad opti o n 65 - 66 57 - 58 59 - 60 61 - 62 63 - 64 v 0 v 1 v 2 v 3 v 4 supp l y lcd driv er sup p l y v o lta ges. t he volta ge d e termine d b y lc d cell is imped anc e-co nverted b y a re sistive dr iver or an oper ation a m plifier for appl icati on. vol t ages sho u ld b e accord ing to the follo w i n g re lations hi p: v 0 1 2 3 4 ss w hen the on-c h ip o perati ng p o w e r circu i t is on, the follo w i n g voltag es are sup p li ed to v 1 to v 4 by th e on-ch ip po w e r circuit. voltag e selecti on is performe d b y t he set lcd bi as comman d . lcd bia s v 1 v 2 v 3 v 4 1/5 bias 4/5v0 3 /5v0 2/5v0 1 /5v0 1/6 bias 5/6v0 4 /6v0 2/6v0 1 /6v0 1/7 bias 6/7v0 5 /7v0 2/7v0 1 /7v0 1/8 bias 7/8v0 6 /8v0 2/8v0 1 /8v0 1/9 bias 8/9v0 7 /9v0 2/9v0 1 /9v0 4
nt7502 lcd dri v er su pplies pad no. symbol i/o descriptions 45 - 46 cap1- o capac itor 1- p ad for intern al dc/dc volta g e converter 47 - 48 cap1+ o capac itor 1+ p ad for intern al dc/dc volta g e converter 51 - 52 cap2- o capac itor 2- p ad for intern al dc/dc volta g e converter 49 - 50 cap2+ o capac itor 2+ p ad for intern al dc/dc volta g e converter 43 - 44 cap3+ o capac itor 3+ p ad for intern al dc/dc volta g e converter 41 - 42 v out o dc/dc volta g e converter outp u t 67 - 68 v r i voltag e adj ustment pad. ap pl ies volta ge bet w e en v 0 a nd v ss using a resistive div i de r 5 4 v ext i t h is is the exte rnal in put refer ence vo ltage ( v ref ) for the in ternal voltag e regu lat o r. it is valid on l y w h en e x tern al v ref i s u s ed. v ext must be dd2 w hen usi ng int e rnal v ref , thi s pad must be nc 8 2 t m p s i selects temper ature coeffici en t of the referen c e voltag e t m ps = 0: -0.05% / ref vrs = 1: using the interna l v ref 5
nt7502 syste m bu s c o n n ectio n pad s pad no. symbol i/o descriptions 17 - 24 d0 - d7 (si) (scl) i/o t h is is an 8-bit bi-dir ection al d a ta bus that co nnects to an 8- bit or 16-b i t standar d mpu data bus. w hen the seri a l interface is se lected (p/s = ?l?), then d7 se rves as the seri al data in put terminal (si) an d d 6 serves as the serial clock in put terminal (scl) at this time, d0 to d5 ar e set to hig h impe da nce. w hen the chi p select is in activ e , d0 to d7 are set to high imp eda nce. 1 2 a 0 i t h is is connected to the le ast signific ant bit o f the normal m p u addr ess bu s, and it determ i n e s w h eth e r the data bits are d a ta or a comm and a0 = ?h? indica ting that d0 to d7 are d i spl a y data, and a0 = ?l? indicat i ng that d0 to d7 are co ntrol data. 11 res i w hen res is set to ?l?, the settings are initialized. t he reset operation is p e rfor med b y the res signal lev e l. 8, 9 1 cs cs2 i t h is is the chip select sign al. w hen 1 cs = ?l? and cs2 = ?h?, th en the chi p select bec omes active, and data/command i/o is enabled. 15 rd (e) i w hen con nect ed to an 8 080 mpu, it is active low . t h is pad is con nected to the rd signa l of the 80 80mpu, an d the nt 7502 data bus is i n a n output status w h en this si gn al is ?l?. w hen con nect ed to a 68 00 s e ries mpu, this is active high. t h is is used as an ena ble cl oc k i nput of the 680 0 series m p u. 14 wr ( w / r ) i w hen con nect ed to an 8 080 mpu, this is active low . t h is terminal co nn ects to the 808 0 mpu wr signal. t he signa ls on the data bus ar e la tched at the rising e d g e of the wr sign al. w hen con nect ed to a 68 00 s e ries mpu, this is the read/ w r it e control si gna l input termi nal. w hen w r / = ?h?: r ead w hen w r / = ?l?: write 7 5 c 8 6 i t h is is the mpu interface s w i t ch terminal c86 = ?h?: 680 0 series mpu i n terface c86 = ?l?: 808 0 mpu interfac e 7 6 p / s i t h is is the paralle l data i nput/ s erial d a ta in pu t s w itch termin a l p/s = ?h?: parallel d a ta in put p/s = ?l?: serial data i nput t he follo w i n g a ppli e s de pen di ng on the p/s status: p / s d a t a/c o m m a n d d at a r ead / w ri t e s e ri a l c l oc k "h " a 0 d 0 to d 7 " l " a 0 s i (d 7 ) w r i t e o n l y sc l (d 6) rd wr w hen p/s = ?l?, d0 to d5 are hz . d0 to d5 ma y b e ?h?, ?l? or open. rd (e) and wr ( w r / ) are fi xe d to either ? h ? or ?l ?. with serial data input, ram displ a y d a ta read ing is not supp orted. 7 3 c l s i t e rminal is use d to select w h e t her ena ble or disab l e the d i s p la y clock i n ter nal oscill ator circui t. cls = ?h?: inte rnal osci llator c i rcuit is ena bl e d cls = ?l?: internal osci llator c i rcuit is disa ble d (requir e s e x t e rnal i n p u t). w hen cls = ?l?, input the di spla y clock thr oug h the cl p ad. 6
nt7502 sy s t em bus conne c t ion pa ds (c ontin ue ) pad no. symbol i/o description 7 2 m / s i t h is terminal selects the mast er/slave o perat ion for the nt 7502 ch ips. master oper ati on outp u ts the timing sig nals t hat are req u ire d for the lcd d i spla y, w h il e slave op e r ation in puts the timing sign al s require d for the liq uid cr ysta l displ a y, s y nc hro n izi ng the liq ui d cr y s ta l displ a y s y st e m . 4 c l i / o t h is is the displa y c l ock in put terminal. w hen the nt 7502 ch ips are used i n master /slave mod e , the vario u s cl terminals must be con necte d. 3 f r i / o t h is is the liquid cr y s tal alte rnating curr ent signal i/o terminal m/s = ?h?: output. m/s = ?l?: input. w hen the nt 7502 ch ip is use d in master/sla ve mode, the v a rious f r term inals must be conn e c ted. 5 dof i/o t h is is the liqui d cr y s tal displ a y bl anki ng co ntrol termina l. m/s = ?h?: output. m/s = ?l?: input. w hen the nt 7502 ch ip is use d in master/sla ve mode, the v a rious dof terminals must be conn e c ted. 2 f r s o t h is is the output terminal for the static drive. t h is terminal is onl y en abl ed w h en th e static indicat o r disp l a y is on in master oper ati on mod e , and i s used in co nju n ction w i t h the f r terminal. 8 0 i r s i t h is terminal selects the resis t ors fo r the v0 voltag e leve l a d justme nt irs = ?h?, use the intern al res i stors. irs = ?l?, do n o t use the inter nal resist ors. t he v0 voltage level is reg u l a ted b y an e x t e rnal resistiv e vo ltage d i vid e r attached to the vr terminal. t h is pad is ena bled onl y w h en the ma ster op eratio n mode i s selected. it is fixed to eit her ?h? or ?l? w hen the sl ave o perati on mod e is selecte d . 78 hpm i t h is is the po w e r control termi nal for the po wer supp l y c i rcui t for liquid cr y s tal dr ive. hpm = ?h?, normal mode hpm = ?l?, high po w e r mode t h is pad is ena bled onl y w h en the mast er op eratio n mode i s selected. it is fixed to eit her ?h? or ?l? w hen the sl ave o perati on mod e is selecte d . 7
nt7502 liqu id cry s ta l dri v e pa ds pad no. symbol i/o description 134 - 26 5 seg0 - 131 o segme n t signa l output for lc d displ a y 101 - 13 2 266 - 29 7 com31 - 0 com32 - 63 o common si gn a l output for lc d displ a y w hen in maste r /slave mod e , the same si gna l is output b y bo th master and slave 133, 29 8 coms o t hese are the com output terminals for the indicator. both te rminals o u tp ut the same signal no con nect the s e terminals if t h e y are n o t used w hen in maste r /slave mod e , the same si gna l is output b y bo th master and slave configura t io n pa ds pad no. symbol i/o description 27, 28 dut y0, du t y 1 i select the lc d driver dut y duty1 duty0 lcd driv e r dut y 0 0 1/33 0 1 1/49 1 0 1/55 1 1 1/65 t est pad s pad no. symbol i/o description 90 t e st 3 i t e st pads, and must be conn ected to v dd 1, 6, 84 - 89 92 - 100 nc nc pads, n o conn ection for u s er 8
nt7502 function al descrip tion micro p r o cess o r in terface interface t y p e selectio n t he n t 7502 can transfer dat a via 8-bit bi-d i r ection al data bus (d7 to d0) or via serial d a ta input (si). w hen hig h or lo w is selecte d for the parit y of p/s pad, either 8-b i t paral lel d a ta in put or serial dat a input can b e selecte d as sho w n in t able 1. wh en serial d a ta in pu t is selected, the ram data ca nnot be re ad o u t. ta ble . 1 p / s t y p e 1 cs c s 2 a 0 rd wr c86 d7 d6 d0 to d5 h p a r a l l e l i n p u t 1 cs c s 2 a 0 rd wr c86 d7 d6 d0 to d5 l s e r i a l in p u t 1 cs c s 2 a 0 - - - s i s c l ( h z ) ?-? must alw a y s be high or lo w pa ra lle l input w hen the nt 7502 se lects p a r alle l in put (p/s = high), the 808 0 se ri es mi croprocess o r o r 6800 s e ries microproc esso r can b e selecte d b y c a using th e c86 p ad to go hi gh o r lo w as sho w n in t able 2. ta ble . 2 c8 6 t y pe 1 cs c s 2 a 0 rd wr d0 to d7 h 680 0 micropr o c essor bus 1 cs c s 2 a 0 e w r / d0 to d7 l 808 0 micropr o c essor bus 1 cs c s 2 a 0 rd wr d0 to d7 data bus signals t he n t 7502 id entifies the d a t a bus sig nal ac cordin g to a0, e, w r / ( rd , wr ) signals. ta ble . 3 common 680 0 process o r 808 0 process o r a0 ( w / r ) rd wr f unction 1 1 0 1 reads disp la y data 1 0 1 0 w r i t e s displa y d a t a 0 1 0 1 r e a d s status 0 0 1 0 w r ites control data in i n terna l register. (com mand) serial interface (p/s is lo w ) w hen the seri a l interface h a s bee n selecte d (p/s = ?l?), then w h e n the chi p is in active st ate ( 1 cs = ?l? and cs2 = ?h?), th e serial data inp u t (si) and the s e rial c l ock i n p u t (scl) can be r e ce ive d . t he serial data is rea d from the ser i a l data inp u t pi n in th e rising e d g e of the seria l clocks d7, d6 throug h d0, in this ord e r. t h is data is converte d to 8 bits of parall e l data in the ris i n g edg e of eighth ser i al clock for proce ssing. t he a0 input is used to deter mine w h ether o r the serial data input is displ a y data, and w h e n a0 = ?l? then the data is com m and data. t he a0 input is read a n d used for det ec tion ever y 8th r i sing e d g e of the serial cl ock a fter the chip be comes active. f i gure 1 is the serial i n terface signa l chart. 9
nt7502 cs2 si scl a0 1 cs d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 12 34 5 6 7 8 9 1 0 11 12 13 14 figure . 1 w hen the chi p is not active, the shift registers and the co unt er are reset to their in itial state s . read in g is not possib l e w h il e i n serial i n terfac e mode. cautio n is r e q u ired on t he s c l sig n a l w h e n it comes t o line- en d reflect i ons and e x ter nal nois e . w e recomme nd t h e oper ation b e re checke d on the actual eq uipm ent. chip select in puts t he n t 7502 h a s t w o c h ip se l e ct pads. 1 cs and cs2 can i n terface to a micro p rocess or w h e n 1 cs is lo w a nd c s 2 is hig h . w hen these p a d s are set to an y ot her comb i natio n, d0 to d7 are hi gh imp eda nce an d a0 , e and w r / inputs are dis abl ed. w hen seri al in put interface is selecte d . the shift register an d counter ar e reset. a c c e ss to dis p lay d a ta r a m an d in tern al reg i sters t he n t 7502 can perform a series of pipeli ne processi ng bet w e en lsi?s usi ng the bus hold e r of the internal data bus in order to match the o per ating fre que nc y of displ a y ra m and i n tern al r egist ers w i t h th e micropr ocess o r. f o r exampl e, the micropr o c essor reads data fro m displa y ram in the first r ead (dumm y ) c y cl e, stores it in the bus ho lder, and out puts it onto s y stem b u s in the ne xt data rea d c y cl e. also, the microprocess o r temporari l y stores displ a y data in the bus hold e r, and stores it in displ a y ram u n til the ne xt data w r it e c y cle starts. w hen vie w e d from the micropr ocessor, the n t 7502 access spee d gr eatl y d epe nds on the c y cl e time rath er than access time to the displ a y ra m (t ac c ). t h is vie w s h o w s the data transfer spee d to / from the microproc es sor can increas e. if the cy cl e time i s inap pro p riate, t he micro p roce ssor can ins e rt the nop instru ction t hat is e q u ival ent to the w a it c y c l e set u p. ho w e v e r, there is a restriction i n th e disp la y r a m read s equ enc e. w hen a n a ddre ss is s e t, the spec ified a ddre ss data is not output at th e immedi atel y fol l o w i ng re ad i n s t ruction. t he address d a ta is output d u rin g the seco nd d a ta read. a sin g l e dumm y rea d must be inserte d after address setu p a nd after the w r i t e c y cle (ref e r to f i gure 2 ). 10
nt7502 n n n+1 n+2 data bus holder mpu internal timing incremented n n+1 n n+1 n+2 preset n set address n dummy read data read address n data read address n+1 n address preset read signal column address r/w e a0 f i gure. 2 bus y flag w hen the bus y flag is ?1?, it indicates that the nt 7502 chip i s runni ng inter nal pr ocesses, and at this tim e no comma nd asi d e from a status read w i ll be rec e iv ed. t he bus y fla g is o u tput ted to d7 pad w i t h the r ead i n struction. if the c y c l e time (t cyc) is maintained, it i s not necessar y t o check for this flag befor e each co mma nd . t h is makes vast improveme n ts in mpu process i n g capa biliti e s po ssible. displa y data r a m displ a y data r a m t he displa y d a t a ram is ram that stores the dot data for the displa y. it has a 65 (8 page * 8 bit+ 1)*1 32 bit structure. it is possib l e to acc e ss the d e sire d bit b y s pecif ying th e pa ge a ddre ss and th e column ad dre ss. because, a s is sho w n in f i gure 3 , the d7 t o d0 di spla y data from the mpu c o rre spon ds to the li qui d cr ystal dis p la y c o mmon d i rection, th ere a r e fe w co nstrai nts at the time of dis p la y commo n dir e ction, a nd the r e are fe w c o n s trai nts at the ti me of disp la y d a ta transfer w h en multi p le nt 750 2 chips ar e used, thus displ a y st ructures w i th a high degr ee of freedom ca n b e created e a sil y . moreover, reading from and w r it ing to the display ram from the mpu side is performed through the i/o buffer, w h ic h is an inde pe nde nt o perati on from s i gna l rea d i ng fo r the liq uid cr ys tal driver. c ons equ entl y , eve n if the dis p la y d a ta ram is acc e sse d as ynchr ono usl y dur in g liq uid cr y s tal d i spl a y , it w i l l not caus e advers e effects on the displ a y (suc h as flic kering). 0 1 0 1 d0 d1 d2 d3 d4 com0 com1 com2 com3 com4 display data ram display on lcd 11 1 00 0 000 0 11 1 00 0 0 0 0 0 0 figure . 3 11
nt7502 the pa ge a d d r e s s circ uit as sho w n i n f i gure 4, pa ge a ddress of the d i spla y d a ta ra m is specified t h rou gh the pa ge addr ess se t command. t he pa g e addr ess must be spec ified a g a in w h en ch an ging pag es to perform acces s . page a ddress 8 (d3, d2, d1, d0 = 1, 0, 0, 0,) is the page fo r the ram regi on use d ; onl y d i spla y d a ta d0 is used. t h e co lu mn a d d r ess as sho w n in f i gure 4, the dis p la y data ra m column a ddres s is specified b y t he co l u mn a ddress set co mmand. t he specifie d column a ddres s is increment ed (+ 1) w i th e a ch disp la y da ta r ead / w r ite command. t h is allo w s the mpu displ a y d a ta to b e accesse d conti nuo usl y . more over, the incr iminatio n of column addr esse s stops w i th 83h, becaus e the column a d dress is inde pe nde nt of the pa ge a ddr ess. t hus, w h en movi ng, for exam pl e, fro m pag e0 co lu mn 83h t o pa ge 1 c o lum n 0 0 h, it is necess a r y to r e specif y b o th the pa ge a ddre ss and the col u mn addr ess. f u rthermore, a s is sho w n i n t able 4, the ad c command (s egme n t driver directio n select command) can be used to reverse the relatio n sh ip b e t w e e n the disp l a y data ram c o lumn ad dress and th e se gme n t outp u t. beca use of th is, the constrai nts on t he ic la yout ca n be minimiz ed w h e n the lcd mo d u le is ass e mbl ed. ta ble . 4 seg output seg0 seg131 adc ?0? 0 (h) t h e l i n e a d d r ess cir c u i t t he line addr e ss circuit, as sho w n i n t able 4, specifies the line ad dress r e latin g to the com out put w hen the co nten ts of the displ a y d a ta r a m are displa yed. using the d i spla y start line addr ess set command, w h at is normall y th e top line of the di spla y can be s pecifi e d. t h is is t he com0 output w h en the comm o n outp u t mode i s normal, a nd t he com63 out put for nt 7502 , w h en the common o u tput mode is r e verse d . t he d i spla y ar ea is a 65- lin e are a for the nt 7502 from t he disp la y start line ad dre ss. if the line ad d r esses are ch ang ed d y n a mi call y usi ng the di spla y start l i ne a ddress s e t command, screen scrol lin g, pag e s w a p p i n g , etc. can be p e rform ed. 12
nt7502 relatio n s h i p b e t w een d i sp la y d a ta r a m an d ad d r ess. (if initial d i sp la y lin e is 1dh) page ad dr e s s d ata line add r ess d0 00 d1 01 d2 02 d3 03 d4 04 d5 05 d6 06 d3 , d 2 , d1 , d 0 0 , 0 , 0, 0 d7 07 d0 08 d1 09 d2 0a d3 0b d4 0c d5 0d d6 0e 0 , 0 , 0, 1 d7 pa g e 1 0f d0 10 d1 11 d2 12 d3 13 d4 14 d5 15 d6 16 0 , 0 , 1, 0 d7 pa g e 2 17 d0 18 d1 19 d2 1a d3 1b d4 1c d5 1d d6 1e 0 , 0 , 1, 1 d7 pa g e 3 1f d0 20 d1 21 d2 22 d3 23 d4 24 d5 25 d6 26 0 , 1 , 0, 0 d7 pa g e 4 27 d0 28 d1 29 d2 2a d3 2b d4 2c d5 2d d6 2e 0 , 1 , 0, 1 d7 pa g e 5 2f d0 30 d1 31 d2 32 d3 33 d4 34 d5 35 d6 36 0 , 1 , 1, 0 d7 pa g e 6 37 d0 38 d1 39 d2 3a d3 3b d4 3c d5 3d d6 3e 0 , 1 , 1, 1 d7 pa g e 7 3f 1, 0 , 0 , 0 d 0 p ag e 8 d0= ?0? 00 01 02 81 82 83 col u m n add res s ad c d0= ?1 ? 83 82 81 02 01 00 lcd out seg0 seg1 seg2 seg1 2 9 seg1 3 0 seg1 3 1 page0 com output co m0 co m1 co m2 co m3 co m4 co m5 co m6 co m7 co m8 co m9 co m1 0 co m1 1 co m1 2 co m1 3 co m1 4 co m1 5 co m1 6 co m1 7 co m1 8 co m1 9 co m2 0 co m2 1 co m2 2 co m2 3 co m2 4 co m2 5 co m2 6 co m2 7 co m2 8 co m2 9 co m3 0 co m3 1 co m3 2 co m3 3 co m3 4 co m3 5 co m3 6 co m3 7 co m3 8 co m3 9 co m4 0 co m4 1 co m4 2 co m4 3 co m4 4 co m4 5 co m4 6 co m4 7 co m4 8 co m4 9 co m5 0 co m5 1 co m5 2 co m5 3 co m5 4 co m5 5 co m5 6 co m5 7 co m5 8 co m5 9 co m6 0 co m6 1 co m6 2 co m6 3 co m s start figure . 4 13
nt7502 the dis p la y da ta la tc h circuit t he displa y dat a latch circuit is a latc h that te mporari l y store s the d i spl a y d a ta o u t put to t he l i qu id cr ysta l driver circu i t from the displ a y data r a m. becaus e the di spla y n o rmal/re verse status , di spla y on/of f status, and dis p la y al l poi nts on/of f commands co ntrol on l y th e data w i th in the latch, the y do n o t chang e t he data w i th in the displ a y data r a m itself. the oscillator circuit t h is is a cr-type oscill ator t hat produces the displa y cl ock. t he oscillator circuit is onl y en able d w h e n m/s = ?h? and cl s = ? h?. w hen cls = ?l? the oscill atio n stops, and th e disp l a y clock is input thro ug h the cl termi nal. displa y timing generator circuit t he displa y tim i ng ge nerat or circuit gener ates the timing sign al to the line ad dress circuit an d the displ a y d a ta latch circuit us i n g the displ a y cl oc k. t he displa y data is latched i n to the displa y data latch circu i t synchro n iz ed w i th the disp la y c l ock, and is output to the data driv er output termi nal. re adi ng to the displ a y dat a liq uid cr ystal driver circ u i ts is complete l y ind epe nde nt of acc ess t o the disp la y d a ta ram b y the mpu. cons e q uentl y , eve n if the disp la y d a ta ram is acce ssed as ync h ro nousl y duri ng l i qui d cr y s tal d i spl a y , there is abso l u t el y n o adv erse effect (such as flickering) o n the dis p la y. moreover, the displ a y timin g g ener ator ci rcuit gen erates the c o mmon timi ng and th e liq ui d cr y s tal altern atin g current si gna l (f r) from the disp la y cl ock. it gene rates a driv e w a veform usi ng a 2 fr ame a l ter natin g curre nt drive meth od, as is sho w n i n f i gure 5 , for the liqu i d cr ystal dr ive circ uit. cl fr com0 com1 ram data segn v 0 v 1 v4 v ss v 0 v 1 v4 v ss v 0 v 2 v3 v ss 60 6 65 64 61 62 63 64 65 23 4 5 1 234 5 1 6 figure . 5 w hen multi p le nt 7502 chips are use d , the sl ave chi p s must be sup p li ed w i t h the dis p la y ti ming si gna ls (f r, cl, dof ) from the master chip[s]. t able 5 sho w s the status of the f r , cl, and dof signals. ta ble . 5 operatin g mod e f r cl dof master (m/s = ?h?) t he internal os cillator circ uit is enab led (c ls = ?h?) t he internal os cillator circ uit is disabl ed (c ls = ?l?) output output output input output output slave (m/s = ?l?) t he internal os cillator circ uit is disabl ed (c ls = ?h?) t he internal os cillator circ uit is disabl ed (c ls = ?l?) input input input input input input 14
nt7502 t able 6 sho w s the relati onsh i p bet w e e n oscil l a tion freq uenc y an d frame fre que nc y ta ble . 6 dut y i t e m f cl f fr on-chip osc illa tor is used f osc / 6 f cl /(2 x 65) 1/65 on-chip osc illa tor is not used extern al i nput f cl f cl /(2 x 65) on-chip osc illa tor is used f osc / 8 f cl /(2 x 55) 1/55 on-chip osc illa tor is not used extern al i nput f cl f cl /(2 x 55) on-chip osc illa tor is used f osc / 8 f cl /(2 x 49) 1/49 on-chip osc illa tor is not used extern al i nput f cl f cl /(2 x 49) on-chip osc illa tor is used f osc / 1 2 f cl /(2 x 33) 1/33 on-chip osc illa tor is not used extern al i nput f cl f cl /(2 x 33) common out put con t rol ci rc uit t h is circuit controls the relatio n ship b e t w e e n the number of common outp u t and specifi e d dut y rati o. common outp u t mode select instructi on spec ifies th e scann ing d i re ction of the co mmon outp u t pads. ta ble . 7 common out p u t pa ds duty s t a t u s com [0-15] com [16-23] com [24-26] com [27-36] com [37-39] com [40-47] com [48-63] coms n o r m a l c o m [ 0 - 1 5 ] n c com[16-31] 1/33 r e v e r s e c o m [ 3 1 - 1 6 ] n c com[15-0] coms n o r m a l c o m [ 0 - 2 3 ] n c c o m [ 2 4 - 4 7 ] 1/49 r e v e r s e c o m [ 4 7 - 2 4 ] n c c o m [ 2 3 - 0 ] coms n o r m a l c o m [ 0 - 2 6 ] n c c o m [ 2 7 - 5 3 ] 1/55 r e v e r s e c o m [ 5 3 - 2 7 ] n c c o m [ 2 6 - 0 ] coms n o r m a l c o m [ 0 - 6 3 ] 1/65 reverse com[63-0] coms t h is is a 197-c han nel mu ltipl e xes th at gen er ate volta ge lev e ls for drivi ng t he li qui d cr ysta l. t he combi nat ion of the disp l a y d ata, the com scan signa l, and th e f r signal pr od uc es the li qui d cr y s tal dr ive vo ltage o u tput. f i gure 6 sh o w s exam pl e of the seg and com output w a ve form. configura t io n se tting t he n t 7502 h a s t w o optio nal configur at ions, configur ed b y dut y0, du t y 1 dut y 1 , du t y 0 c o m m o n s e g m e n t v 1 v 2 v 3 v 4 1, 1 65 132 8/9v0, 6/7v0 7/9v0, 5/7v0 2/9v0, 2/7 v0 1/9v0, 1/7v0 1, 0 55 132 7/8v0, 5/6v0 6/8v0, 4/6v0 2/8v0, 2/6 v0 1/8v0, 1/6v0 0, 1 49 132 7/8v0, 5/6v0 6/8v0, 4/6v0 2/8v0, 2/6 v0 1/8v0, 1/6v0 0, 0 33 132 5/6v0, 4/5v 0 4/6v0, 3/5v0 2/6 v0 , 2/5v0 1/6v0, 1/5v0 15
nt7502 v dd fr com0 com1 com2 seg0 seg1 com0 - seg0 com0 - seg1 v ss com0 com1 com2 com3 com4 com5 com6 com7 com8 com9 com10 com11 com12 com13 com14 com15 seg2 v 1 v 4 v ss v 2 v 0 v 3 v 1 v 4 v ss v 2 v 0 v 3 v 1 v 4 v ss v 2 v 0 v 3 v 1 v 4 v ss v 2 v 0 v 3 v 1 v 4 v ss v 2 v 0 v 3 v 1 v 4 v ss v 2 v 0 v 3 v ss v 4 v 3 v 0 v 2 v 1 -v 4 -v 1 -v 0 -v 3 -v 2 v ss v 4 v 3 v 0 v 2 v 1 -v 4 -v 1 -v 0 -v 3 -v 2 figure . 6 16
nt7502 the po w e r su pply circ uit t he po w e r su p p l y circu i ts are lo w - p o w e r c o n s umptio n po w e r suppl y circuit s that ge nerate the vo lta ge le vels req u ir ed f o r th e liqu i d cr y s ta l drivers. t h e y co mprise booster circuits, voltage regul ator circuits, and volta ge follo w e r circuits. t h e y are on l y ena ble d in mas t er operati on. t he po w e r s u p p l y circu i ts can turn the b oost e r circuits, the volt ag e reg u l a tor circuits, a n d the vo ltage fol l o w er c i rcuits on o r of f indepen d entl y t h rou gh th e use of the po w e r contro l set comm and. co nseq uentl y , it is possibl e to ma ke an e x tern al po w e r suppl y a nd the intern al po w e r suppl y fu nction some w hat in p a rall el. t able 7 sho w s the po wer control set comman d 3-bit dat a control functi on , and t able 8 sho w s refer enc e combi natio ns . ta ble . 8 t he control d e tails of each bit of the po w e r cont rol set comma nd status item ? 1 ? ? 0 ? d2 booster circuit control bit on off d1 volta ge reg u lator circu i t (v regul ator circu i t) control bit o n of f d0 voltage follo w er circuit (v/f circuit) control bit on off ta ble . 9 use settings d2 d1 d0 step-up circuit voltag e regul ator circuit v/f circuit ex ternal voltag e inp u t step-up voltag e s y stem terminal 1. only the internal po w e r supply is used 1 1 1 o o o v dd2 u s e d 2. only the v regulator circuit and the v/f circuit are use d 0 1 1 x o o v out , v dd2 o p e n 3. onl y th e v/f circuit is used 0 0 1 x x o v 0 , v dd2 o p e n 4. only the ex ternal po w e r supply is used 0 0 0 x x x v 0 to v 4 o p e n *t he ?step-up s y stem termin a l s? refer cap1 + , cap1-, cap2+ , cap2-and cap3+ . *w hile other c o mbinati ons, n o t sho w n ab ove, are als o p o ssib l e, these c o mbi natio ns are not recommen d e d beca u se th e y hav e no practic a l us e. t he step-up voltag e circuits using th e step- up volta ge circ uits w i t h in th e nt 7502 chips i t is possible to prod uct 4x, 3 x , 2x step-u p s o f the v dd2 -v ss vo l t a ge levels 17
nt7502 4x step-up voltage relationships 3x step-up voltage relationships 2x step-up voltage relationships cap3+ cap1- cap1+ nt7502 2x step-up voltage circuit 3x step-up voltage circuit 4x step-up voltage circuit v ss v out v dd2 = 3v v ss = 0v v out = 4 x v dd2 = 12v v dd2 = 3v v ss = 0v v out = 3 x v dd2 = 9v v dd2 = 3v v ss = 0v v out = 2 x v dd2 = 6v cap2- cap2+ c1 c1 cap3+ cap1- cap1+ nt7502 v ss v out cap2- cap2+ c1 c1 cap3+ cap1- cap1+ nt7502 v ss v out cap2- cap2+ c1 c1 c1 c1 c1 figure . 7 the volta g e r e gula t or circ uit t he step-up voltag e gen erat ed at vout outputs the liq ui d cr y s tal driver v o ltag e v0 thro u gh the vo ltag e regul ator circu i t becaus e the n t 7502 chips h a ve a n inter nal hig h -accur a c y fixe d volta ge p o w e r su ppl y w i th a 64-l e vel el ectronic vo lum e function a nd in ternal resistors for the v0 voltage reg u lator, s y stems ca n be construct e d w i tho u t hav ing to i n clu de high- accur a c y voltag e regu lat o r circuit comp one nts. moreover, in t he nt 7502, three t y p e s of thermal gra d ie nts have b e e n prepar ed as vreg options: (1) appr o x imate l y ?0.05 %/ (2) appr o x imate l y ?0.2%/ , a nd (3) exter nal i n p u t (suppl ied to the v ext terminal). w h en th e v0 vo ltag e reg u l ato r in tern al resisto r s a r e used t h rough the use of the v0 voltage reg u lator i n terna l resistor s and the e l ectr onic vol u me fu nction the li qu i d cr y s tal p o w e r suppl y v o lta g e v0 can be c ontroll ed b y c o mmands al on e ( w it hout a d d i ng an y e x tern al r e sistors), maki ng it poss i bl e to adjust the li qui d cr y s tal dis p l a y br ightn e ss. t he v0 voltage can be calcu l at ed usin g equ ati on a-1 over the range w h ere t ou v 0 v $ . v0 = ( 1+ rb/ r a)*v ev = ( 1+r b /ra)* (1-(63- % )/ 162)*v reg (equat io n a-1) - + v ev r a v ss v out r b v o v ev (constant voltage supply + electronic volume) 18
nt7502 v reg is t he i c int e rna l f i xed vo lt age su ppl y, a nd it s volt ag e a t t a = 25 is as sho w n i n t able 10. t a b l e. 10 equi pment t y p e t m ps vrs t hermal gradient unit s v reg i n t e rnal p o w e r supp l y 0 1 -0. 05 %/ 2. 1 i n t e rnal p o w e r supp l y 1 1 -0. 2 %/ 2. 1 ext e rn al i nput * 0 - - v ext is set t o 1 lev e l of 64 possi bl e leve ls b y t he elect r o n ic vol u me f unct i o n de pen din g on t h e dat a set in t he 6-bit el ect r onic vo lum e regist er. t able 10 sho w s t he value f o r dependin g on t he el ect r onic volum e regist er set t i ngs. ra/ r b is t h e v0 volt age regulat o r int e rn al resist o r rat i o, and can be set t o 8 dif f e rent lev e ls t h r oug h t he v0 vo lt age re gul at or int e rn al resist o r rat i o set comm and. t he (1+ r b/ ra) rat i o assumes t he valu es sho w n in t able1 1 dep end ing on t he 3-b i t dat a set t i ngs in t he v 0 volt ag e regu l a t o r int e rn al resist o r rat i o regist er. t a b l e. 11 d 5 d 4 d 3 d 2 d1 d0 v 0 0 0 0 0 0 0 0 m i n i m u m 0 0 0 0 0 1 1 : 0 0 0 0 1 0 2 : : : : : 1 0 0 0 0 0 32 (def a u lt ) : : : : : 1 1 1 1 1 0 6 2 : 1 1 1 1 1 1 6 3 m a x i m u m v0 volt ag e reg u lat o r i n t e rna l resist anc e rat i o regist er val ue and (1+ r b /r a ) rat i o (ref ere n c e valu e) t a b l e. 12 regist er equi pment t y p e b y t hermal gradie n t [ u nit s : % / ] d2 d1 d0 1. -0. 05 2. -0. 2 3. v reg ext e rna l i nput 0 0 0 3. 0 3. 0 1. 5 0 0 1 3. 5 3. 5 2. 0 0 1 0 4. 0 4. 0 2. 5 0 1 1 4. 5 4. 5 3. 0 1 0 0 5. 0 5. 0 3. 5 1 0 1 5. 5 5. 5 4. 0 1 1 0 6. 0 6. 0 4. 5 1 1 1 6. 4 6. 4 5. 0 19
nt7502 t he v0 volt age is a f unct i on o f t he v0 volt ag e regu lat o r int e r nal resist or rat i o regist er and t he elect r o n ic v o lumn re gist er. set up e x am ple : w hen select i ng t a = 2 5 and v0 = 7v f o r an nt 7502 mo del o n w h ic h t he t e mperat ur e gradi ent = -0. 05% , using t h e eq ua t i on a-1, t he f o l l o w i ng set u p is enab led. t a b l e. 13 regist er cont e n t s d5 d4 d3 d2 d1 d0 f o r v0 volt age regul at or - - - 0 1 0 elect r onic v o lu me 1 0 0 1 0 1 w hen t he v0 volt ag e regul at o r int e rnal resist ors or t he elect r onic vol u me f unct i on is use d , it is necessar y t o at least set th e volt ag e regu lat o r circuit and t he volt a ge f o ll o w er circu i t t o an oper at ing mode usi ng t h e po w e r co nt r o l set comma nds. moreover, it is necess a r y t o p r ovide a volt ag e f r om vou t w h en t h e boos t e r circuit is off . t he vr t e rminal is en abl ed o n l y w h en t he v 0 volt ag e reg u l a t o r int e rn al re sist ors are not used (i. e . t he i r s t e rmina l = ?l?). w hen t he v0 v o lt ag e regu lat o r int e rna l resist ors are use d (i. e . w h en t h e i r s t e rnimal = ?h ?), t hen t he vr t e rminal is lef t ope n . becaus e t he in put imped anc e of t he vr t e rminal is hi gh, it is nec ess a r y t o t a ke int o consi d e r at ion short le a d s, shield ca bl es, et c. t o handl e noise. the li qui d cry s t a l volta g e ge ne ra tor circ uit t he v0 volt ag e is pro duc ed b y a resist iv e vo lt age divi der w i t h in t h e i c , a nd can b e pr oduc ed at t h e v1, v 2 , v3, an d v4 v o lt ag e levels re quir e d f o r liquid cr yst a l drivi ng. moreover, w h e n t he vo lt age f o l l o w e r chan ges t he impe da nce, it provides v1, v2, v 3 , and v4 t o t he l i quid cr yst a l dri v e circuit . 1/ 9 b i as or 1/ 7 bi as f o r nt 7502 can be select e d . high po w e r m ode t he po w e r su p p l y circu i t eq uip ped in t h e nt 7502 c h ips has ver y lo w po w e r consum pt ion ( normal m o d e : hpm = ?h?). ho w e ver f o r lcds or pa nels w i t h lar g e loads, t h is lo w - po w e r p o w e r suppl y ma y ca use disp la y qu alit y t o d egra d e . w hen t h is occurs, set t i ng t he hpm t e rminal t o ? l ? (hi gh p o w e r m o d e ) can im prove t he qu alit y of t he dis p l a y . w e recommen d t h at t he dis p la y b e checke d on act ual e qui pment t o det ermin e w het her or n o t t o use t h is mode. moreover, if t h e improv ement t o t he dis p la y is inad eq uat e ev en af t e r h i gh p o w e r mo de h a s bee n set , t hen it is necess a r y t o ad d a co mma nd se q u e n c e w hen bu ilt-in po w e r su p p ly is tu rn ed off. f o llo w t h e com m and se que nc e as sho w n bel o w t o t u r n of f the bu ilt -in p o w e r supp l y af t e r t he s y st em ent ers st andb y m ode. 20
nt7502 re fe re nc e pow e r su pply circ uit for dri v i ng lcd pa ne l -w hen not usi n g volt ag e bo ost e r circuit s -w hen usi ng al l lcd po w e r ci rcuit s (volt a g e conve r t e r regul at or a nd f o ll o w er) m/s v out c3+ c2+ c2- c1+ c1- vr v0 v1 v2 v3 v4 c2 c2 c2 c2 c2 ra rb external power supply v dd v ss (i n case of 3x boost i ng circu i t ) m/s v out c3+ c2+ c2- c1+ c1- vr v0 v1 v2 v3 v4 c1 c1 c2 c2 c2 c2 c2 ra rb v dd v ss c1 w hen not usi n g int e rn al lc d po w e r s upp l y c i rcuit s w hen on l y usi ng volt a ge f o ll o w e r m/s v out c3+ c2+ c2- c1+ c1- vr v0 v1 v2 v3 v4 c2 c2 c2 c2 c2 external power supply v dd v ss c2 c1 m/s v out c3+ c2+ c2- c1+ c1- vr v0 v1 v2 v3 v4 external power supply v dd v ss *value of external capacitance item value 1.0 - 4.7 0.47 - 2.2 21
nt7502 reset cir c u i t w hen t he res inpu t f a lls t o ?l?, t h ese lsi reent e r t heir def au lt st at e. t he def au lt set t i ngs are s h o w n bel o w : 1 . disp lay off 2. normal d i spl a y 3. adc select : n o rmal di s p lay ( a dc command d0 = ?l?) 4. po w e r co nt rol r egist er (d2, d 1 , d0) = (0, 0, 0,) 5. regist er dat a c l ear in s e rial i n t e rf ace 6. lcd po w e r su ppl y bi as rat i o 1/ 9 (1/ 65 d u t y ), 1/ 8 (1/ 55, 1/ 49 dut y ) , 1/ 6 (1/ 3 3 dut y) 7. read m odif y w r it e of f 8. st at ic indic a t o r : off st at ic indic a t o r regist er: (d1, d2) = (0, 0) 9. displ a y st art li n e regist er set a t f i rst line 10. colum n ad dres s count er set a t address0 11. page a ddress r egist er set at p age 0 12. common o u t p ut st at us normal 13. v0 volt ag e reg u lat o r i n t e rna l po w e r s upp l y r a t i o set mode c l ear: v0 volt ag e reg u lat o r internal resistor ra t i o re gist er: (d2, d1, d0) = (1, 0, 0) 14. elect r onic v o lu me regist er set mode cle a r elect r onic v o lu me regist er: (d 5, d4, d3, d2, d1, d0) = (1, 0, 0, 0, 0, 0, ) 15. t e st mode cle a r 16. all-in dicat o r- la mps-on of f (all-in dicat o r- la mps on/ o f f command d 0 = ?l?) 17. out put condit i o n of com, seg com: v1 seg: v2 on t he ot her h and, w h en t he reset comman d is used, on l y def au lt set t i ngs 7 t o 15 abov e are put int o ef f e ct . t he mpu int e rf ace (ref er en ce exampl e)?, t he res t e rminal i s conn ect ed t o t he mpu r e set t e rminal, making t he ch ip reinit i a liz e sim u lt an eous l y w i t h t he mpu. at t he t i me of p o w e r u p , it is necess a r y t o r e init i a liz e usi n g t he res terminal. moreover, w h e n t he cont rol si gnal f r om t he m p u is in a hig h i m ped ance st at e, t here ma y b e an overcurre nt condit i o n ; t her ef ore, t a ke measur es t o prevent t he input t e rmi nal f r om ent erin g a high im pe danc e st at e. i n t he nt 7502, if t he int e rn al li quid cr yst a l po w e r sup p l y circ uit is not use d , t hen it is nec es sar y t o a p p l y a ?l? sign al t o t he res t e rminal w h e n t he e x t e rn al li qu id cr y s t a l po w e r suppl y is a ppl ied. even t hou gh t h e oscill at or circ uit oper at es w h ile t he res t e rminal is ?l, ? t he displ a y t i mi ng ge ner at or circuit is st opp ed, and t h e f r , f r s, and dof t e rminals ar e f i xe d t o ?h, ? and t he cl pin is f i xed t o ?h? onl y w h en t he int e rmal osci llat o r circuit is used. t here is no inf l uenc e on t he d 0 t o d7 t e rmin als. 22
nt7502 c o mmands t he n t 7502 uses a combin at ion of a0, rd (e) and wr ( w r / ) signals to identif y data bus signa ls. as the chip analy z es and execut es each command usin g int e rn al t i mi n g clock o n l y re gardl ess of e x t e rnal c l ock, it s processi ng s p e ed is ver y hig h and it s bus y c heck is u s uall y n o t requi red. t he 8080 series micro p rocessor int e rf a c e ent ers a rea d st at us w h en a lo w puls e is input t o t he rd pad an d a w r it e st at us w h en a lo w puls e is input t o t he wr pad. t he 6800 series micropr ocessor int e rf a c e ent ers a read st at us w h en a high pu ls e is input t o t h e w / r pad and a w r it e st at us w h e n a lo w p u lse i s input t o t h is p ad. w hen a hig h pulse is i nput t o t he e pad, t he comm and i s act i vat ed. (f or t i ming, s ee ac char act e ri st ics. ). accordingl y, i n t he c o mmand expla nat i on an d comma nd t a ble, rd (e) beco m es 1(h i gh) when t h e 6 8 0 0 series micr opr ocessor int e rf a c e rea d s st at u s of displ a y dat a. t h is is t he on l y dif f e rent po int f r om t he 808 0 series micro p ro cessor int e rf ac e. t a king t he 808 0 series micro p r ocessor int e rf ace as an e x a m ple, comman d s are e x p l ai ne d bel o w . w hen t he seri a l int e rf ace is se lect ed, in put da t a st art i ng f r om d7 in seq uenc e. command set 1 . disp lay on/ o ff alte rn a t ive l y turn s th e d i splay o n a n d o ff. a0 e rd w r / wr d 7 d 6 d 5 d 4 d 3 d2 d1 d0 s e t t i n g 0 1 0 1 0 1 0 1 1 1 1 d ispl a y o n 0 d i s p l a y o f f w hen t he disp l a y of f comm and is e x ec ut e d w h en i n t he d i spla y all po int s on mode, p o w e r save mod e is ent er ed. se e t he sect ion o n t he po w e r s a ver f o r det ails. 2. set displa y st art line specif i e s line a ddress (ref e r t o f i gure 4) t o det ermine t he i n it ial dis p la y li ne , or com0. t he ram displa y dat a bec omes t h e t op lin e of lcd screen. i t is f o llo w ed b y t h e hi gher n u mber of lines in ascen d i ng or der, corre spon din g t o t h e dut y c y cl e. w hen t h is comman d chan ges t he li n e addr ess, smoot h scrol lin g o r a page ch an g e t a kes plac e. a0 e rd w r / wr d 7 d 6 d 5 d 4 d 3 d2 d1 d0 0 1 0 0 1 a 5 a 4 a3 a2 a1 a0 high-or der b i t a 5 a 4 a 3 a 2 a 1 a 0 line addr ess 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 1 0 2 : : 1 1 1 1 1 0 6 2 1 1 1 1 1 1 6 3 23
nt7502 3. set page ad dress specif i e s pa ge addr ess t o loa d displ a y ram d a t a t o pag e ad d r ess regist er. a n y r a m dat a b i t can be acc e ss ed w h en it s pa ge addr ess an d co lumn a ddress a r e specif i ed. t he disp la y rema i n s unch a n ged even w h en t h e pag e ad dress i s chang ed. pa ge addr ess 8 is t he displ a y ram area d edic a t e d t o t he indicat o r, and onl y d 0 i s valid f o r dat a chan ge. a0 e rd w r / wr d 7 d 6 d 5 d 4 d 3 d2 d1 d0 0 1 0 1 0 1 1 a3 a2 a1 a0 a 3 a 2 a 1 a 0 page a ddress 0 0 0 0 0 0 0 0 1 1 0 0 1 0 2 0 0 1 1 3 0 1 0 0 4 0 1 0 1 5 0 1 1 0 6 0 1 1 1 7 1 0 0 0 8 4. set column address specif i e s colu mn addr ess of displ a y ram. divid e t he col u mn addr ess int o 4 hig her b i t s and 4 l o w e r bit s . set each of t hem successio n . w hen t he micr op rocessor re pea t s t o access t he disp la y ram , t he column a ddress co unt er is increme n t a l b y durin g eac h ac cess unt il a ddr ess 132 is acc e ssed. t he page ad dress is n o t chang ed d u r i ng t h is t i me. a0 e rd w r / wr d 7 d 6 d5 d4 d3 d2 d1 d0 high er bit s 0 1 0 0 0 0 1 a7 a6 a5 a4 lo w e r bit s 0 1 0 0 0 0 0 a3 a2 a1 a0 a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 line addr ess 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 : : 1 0 0 0 0 0 1 1 1 3 1 24
nt7502 5. read st at us a0 e rd w r / wr d 7 d 6 d 5 d 4 d3 d2 d1 d0 0 0 1 b u s y a d c on/off reset 0 0 0 0 bus y : w hen hig h , t he n t 7502 is busy due t o int e rn al oper at ion or reset . an y com m and is reject e d unt il busy goes lo w . t he bus y chec k is not requir e d if enou gh t i m e is provi ded f o r each c y cle. adc: i ndicat e s t he relat i o n sh ip bet w e en ram col u mn addr ess and segme n t drivers. w hen low , t h e displ a y i s reverse d and col u mn a ddress ?13 1 -n? correspon ds t o segment dri v er n. w hen high, t he disp la y is norma l an d colum n addr ess corres pon ds t o segm ent driver n. on/off: indicates w h et her the displ a y is on or off. when lo w , the dis p lay turns on. when hi gh, the displ a y turns off. t h is is t he opp osit e of displa y on/ o f f command reset : indicates the i n itializ ation is i n progress by res signal or b y r e se t command. w hen l o w , t he di spla y is o n . w hen high, t he ch ip i s bein g reset . 6. w r it e displa y dat a w r it e 8-bit dat a in displ a y ra m. as t he column addr ess au t o mat i call y i n cr ement s b y 1 af t e r each w r it e, t he microproc e ssor can cont i nue t o w r it e d a t a of mult ipl e w o rds. a0 e rd w r / wr d 7 d 6 d 5 d 4 d3 d2 d1 d0 1 1 0 w r it e dat a 7. read d i spl a y dat a reads 8- bit d a t a f r om displ a y ram are a specif ied b y column a ddre ss and pag e addr ess. as the colum n ad dress aut omat ic all y i n crement s b y 1 af t e r each w r it e, t he microproce ssor can cont in ue t o read dat a of mult iple w o rds. a sing l e dumm y re ad i s require d immediat el y af t e r column ad dre ss set up. ref e r t o t he displa y ram sect ion of f unc t i ona l descri pt i o n f o r det ails. n o t e t hat no dis p la y d a t a can b e read vi a t he serial i n t e rf ace. a0 rd wr d 7 d 6 d 5 d 4 d3 d2 d1 d0 1 0 1 read dat a 8. adc select chan ges t he r e lat i o n sh ip bet w e en ram col u mn ad dress a nd segm ent dri v er. t he order of segm ent dri v er out put p a d s ca n be reversed b y sof t w a r e . t h is allo w s f l e x ibl e i c la yout duri n g lcd module a ssembl y . f o r det ails, ref e r t o the column ad dr ess sect ion of f i gu re 4. w hen dis p la y d a t a is w r i t t en or read, t h e colum n addr ess is increme n t ed b y 1 as sh o w n in f i gure 4. a0 e rd w r / wr d 7 d 6 d 5 d 4 d 3 d2 d1 d0 0 1 0 1 0 1 0 0 0 0 d w hen d is lo w , rot a t i on is t o t he rig h t (norma l direct io n) w hen d is hi gh , rot a t i on is t o t he lef t (reverse direct io n) 9. normal/ rev e rse disp la y reverses t h e displ a y on/ o f f st at us w i t h o u t re w r it i ng t he c ont ent s of t he displ a y dat a r a m. a0 e rd w r / wr d 7 d 6 d 5 d 4 d 3 d2 d1 d0 0 1 0 1 0 1 0 0 1 1 d w hen d is lo w , t he ram dat a is high, w i t h lcd on pot ent i a l (norma l disp l a y ) w hen d is hi gh , t he ram dat a is lo w , w i t h l cd on pot ent i a l (reverse d i s p la y) 25
nt7502 1 0 . en tire disp lay on f o rcibl y t u r n s t he ent ire dis p l a y on re gard l e ss of t he cont ent s of t he displa y dat a ram. at t h is t i me, t h e cont ent s of th e displ a y dat a r a m are hel d. t h is command has priorit y o v er t he norma l / r everse dis p la y comm and. w hen d is l o w , t h e n o rmal displ a y st at us is provid ed. a0 e rd w r / wr d 7 d 6 d 5 d 4 d3 d2 d1 d0 0 1 0 1 0 1 0 0 1 0 d w hen d is hig h , t he ent ire disp la y on st at us i s provide d . i f t h e ent i re disp la y on comman d is execut e d in t he displ a y o f f st at us, t he lcd pan el ent ers po w e r sav e mode. ref e r t o t he po w e r save sect ion f o r det ails. 11. set lcd bi as t h is command select s t he vol t age bi as rat i o requir ed f o r t h e liqui d cr y s t a l d i spla y. dut y a0 e rd wr d 7 d 6 d 5 d 4 d 3 d2 d1 d0 1/ 3 3 1 / 4 9 1/ 5 5 1/ 6 5 0 1 0 1 0 1 0 0 0 1 0 1 / 6 b i a s 1/ 8 b i a s 1/ 8 b i a s 1/ 9 b i a s 1 1 / 5 bias 1/ 6 bias 1/ 6 bias 1/ 7 bias w r / 12. rea d -mod i f y - w r it e a pair of read- modif y -w rit e and end comma nds must al w a ys be used. once read-m odif y - w rit e is issued, column addr es s is not incr emen t a l b y re ad dis p la y d a t a com m and b u t incre m ent al b y w r it e disp la y dat a command onl y. i t cont inues u n t i l end comman d is issued. w h en t he end is issued, col u mn address ret u rns t o t he address w h en rea d -modif y -w rit e is issued. t h is can reduc e t he microproc essor l oad w h en d a t a of a specif ic dis p la y are a is rep eat ed l y c han ge d duri ng curso r blink i ng or ot he r event s. a0 e rd w r / wr d 7 d 6 d 5 d 4 d3 d2 d1 d0 0 1 0 1 1 1 0 0 0 0 0 not e : an y com m and e x ce pt read/ w r it e displ a y dat a a nd set column add r ess can be issued dur ing re ad-mod i f y -w rit e mode. cursor dis p la y sequ ence set page address set column address read-modify-write dummy read read data write data completed? end yes no data process 26
nt7502 13. end cance l s rea d -modif y -w rit e mode an d ret u rn s column addre ss t o t he origin al address ( w h en rea d -mod if y-w r it e is issue d ) a0 e rd w r / wr d 7 d 6 d 5 d 4 d3 d2 d1 d0 0 1 0 1 1 1 0 1 1 1 0 column address n n+1 n+2 n+3 n+m n read-modify-write mode is selected end return 14. reset t h is command reset s t he displ a y st art line re gist er, column address cou n t e r, page addre ss regist er, and common out p u t mode reg i st er, t he v0 volt age regulat or int e r nal resist or rat i o regist er, t he elect r onic vo lu me regist er, t he st at ic indicat o r mode reg i st er, t he read-mod i f y - w rit e mo de regist er, an d t he t e st mode. t he reset command do es not af f e ct on t h e cont ent s of dis p la y ram. ref e r t o t he reset circuit sect ion of f unct i on de script i on. a0 e rd w r / wr d 7 d 6 d 5 d 4 d3 d2 d1 d0 0 1 0 1 1 1 0 0 0 1 0 t he reset com m and c ann ot in it ializ e l cd p o w e r su ppl y. on l y t he r e set si g nal t o t he res pad can i n it ia lize t h e sup p li es. 15. out put st at us select re gi st er applic ab le t o t he nt 7502. w hen d is hig h o r lo w , t he sc an direct io n of t h e com out put p ad is s e lect a b l e . ref e r t o out put st at us select or circuit in f unc t i on descri p t i o n f o r det ails. a0 e rd w r / wr d 7 d 6 d 5 d 4 d3 d2 d1 d0 0 1 0 1 1 0 0 d * * * d: select s t he scan dir e ct ion of com out put pad d = 0: normal (com0 ? / wr d 7 d 6 d 5 d 4 d3 d2 d1 d0 0 1 0 0 0 1 0 1 a 2 a 1 a 0 when a0 goes lo w , voltage follo w e r turn s off. when a0 goes high, it turns on. when a1 goes lo w , voltage regulat or turns off. when a1 goes high, it turns on. when a2 goes lo w , voltag e booster turns off. when a2 goes high, it turns on. 27
nt7502 17. v0 volt a g e regul at or i n t e rnal res i st or r a t i o set t h is command set s t he v0 volt age reg u l a t o r int e rn al resist o r rat i o. f o r det ails, see e x p l a nat io n und er ?t he po w e r su ppl y circuits?. a0 e rd w r / wr d7 d6 d5 d4 d3 d2 d1 d0 rb / ra ratio 0 1 0 0 0 1 0 0 0 0 0 s m a l l 0 0 1 0 1 0 : : 1 1 0 1 1 1 l a r g e 18. t he elect r onic vol u me (d oubl e b y t e co mmand) t h is command makes it possible t o adj ust t he bright n e ss of t he liqui d cr y s t a l disp la y b y c ont roll in g t he li quid cr yst a l dri v e volt ag e v0 t h ro ugh t he o u t put f r om t he volt ag e regu lat o r circ uit s of t he int e r nal li qui d cr y s t a l po w e r sup p l y . t h is command is a t w o-b y t e command use d as a pair w i t h t he e l ect r on i c volume m o d e set comma n d an d t he e l ect r onic volume re gist e r set command , and bot h com m ands must b e issue d one af t e r t he ot her. t he elect r onic volume m ode set w hen t h is command is input , t he elect r o n ic volume reg i st er set command is enabl ed. once t he elect r onic volume mode ha s bee n set , no ot her comma nd exc ept t he e l e c t r onic vol u me regist er comm and ca n b e us ed. once t he e l ect r onic v o lum e regist er set co mmand h a s be en use d t o set dat a int o t h e re gist er, t hen t h e elect r on ic volu me mode is rel ease d . a0 e rd w r / wr d 7 d 6 d 5 d 4 d3 d2 d1 d0 0 1 0 1 0 0 0 0 0 0 1 elect r onic v o lu me regist er set b y usin g t h is c o mmand t o set six bit s of dat a t o t he e l ect r on i c volum e reg i st er, t he li qui d cr yst a l v o lt a ge v 0 assumes one of t he 64 volt a ge l e vels. w hen t h is com m and is i nput , t he el ect r onic v o lume mo de is releas ed af t e r t he el ect r onic v o lume re gist er has be en set . a0 e rd w r / wr d 7 d 6 d 5 d 4 d3 d2 d1 d0 v 0 0 1 0 * * 0 0 0 0 0 0 s m a l l 0 1 0 * * 0 0 0 0 1 0 0 1 0 * * 0 0 0 0 1 1 0 1 0 * * : : 0 1 0 * * 1 1 1 1 1 0 0 1 0 * * 1 1 1 1 1 1 l a r g e w hen t he el ect r onic vol u me f u nct i on is n o t used, set d5 - d0 t o 10000 0. 28
nt7502 19. st at ic i ndic a t o r (dou ble b y t e comm an d) t h is command cont rols t he st at ic driv e s y st e m indic a t o r d i s p la y. t he st at ic ind i cat o r disp l a y is co nt roll ed b y t h is c o mma nd onl y, an d is ind epe nde nt of ot her dis p la y co n t rol commands . t h is is used w hen one of t he st at ic indic a t o r liqu i d cr yst a l dr iv e el ect r od es i s conn ect ed t o t he f r t e rmina l , and t he ot her is conn ect ed t o t he f r s t e rmin al. a dif f e rent pat t e rn is rec o mmende d f o r t he st at ic in dica t o r elect r od es r a t her t h a n f o r t h e d y namic drive elect r o des. i f the pat t e rn is t o o close, it can r e su lt in d e t e rio r at ion of t he li q u id cr yst a l a nd of t he elect r od es. t he st at ic indicat o r on command is a doubl e - b y t e comma n d paired w i t h t h e st at ic indicat o r regist er set co mmand, and t hus command mus t be execut e d one af t e r t he ot her. (t he st at ic indicat o r of f command is a singl e b y t e co mmand. ) sta t ic in d i ca to r on/of f w hen t he st at ic indicat o r on command is e n t e red, t he st at ic indicat o r reg i st er set command is ena bl ed . once t he st atic indic a t o r on c o mmand has b een ent ere d , n o ot her c o mma nd as ide f r om t he st at ic i ndic a t o r regist er s e t command can b e used. t h is mode is cle a red w hen d a t a is set in t he reg i st er b y t h e st at ic in dicat o r re gist er set command. a0 e rd w r / wr d 7 d 6 d 5 d 4 d3 d2 d1 d0 0 1 0 1 0 1 0 1 1 0 d d = 0 : sta t ic in d i ca to r off d = 1: st at ic i n dicat o r on st at ic i ndicat o r regist er set t h is command set s t w o bit s of dat a int o t h e st at ic indicat o r regist er an d is used t o set t he st at ic indic a t o r int o a bl inki n g mode. a0 e rd w r / wr d 7 d 6 d 5 d 4 d 3 d2 d1 d0 indicator display st a t e 0 1 0 * * * * * * 0 0 o f f 0 1 on (blinki ng at appro x imat el y 0. 5 secon d int e rvals 1 0 on (blinki ng at appro x imat el y 1 secon d int e rv als 1 1 on (const ant l y o n ) * disab l e d bit 20. po w e r sav e (compo un d comman d ) when all displ a y s are turned on durin g di splay off, the po w e r save command is is sued to greatl y r educ e current consum pt ion. if the s t atic indi cators are off, the po w e r sav e command driv es the s y stem into sleep mode. if on, this com m and driv es the s y st em int o st and b y m ode. rele ase t h e s l eep mod e us i ng b o t h t h e po w e r s a ve o f f command (displ a y on c o mmand or e n t i re dis p l a y off command) and set i ndicat o r on command. static indicator off static indicator on power save (display off and entire display on) (sleep mode) (standby mode) power save off (display on or entire displays off ) static indicator on (sleep mode released) (standby mode released) 29
nt7502 slee p mode t h is mode st op s ever y o perat i on of t h e lc d displ a y s y st em, and c an r educ e curre nt cons umpt io n ne arl y t o a st at ic curr e n t value if n o acc e ss is made f r o m t he micropro c essor. t he int e rnal st at us i n t he sle ep mod e is as f o llo w s : (1) st ops t he oscil l a t o r circuit an d lcd po w e r su ppl y circu i t . (2) st ops t he lcd drive, an d out p u t s t he v ss level as t he segm ent / c ommon dr iver out p u t . (3) holds t h e disp l a y d a t a an d op erat io n mode p r ovide d bef or e t he st art of t he sleep m ode. (4) t he mpu can access t he bu il t - in displ a y ra m. st andb y mo de st ops t he oper at ion of t he dut y lcd d i spl a y s y st em an d onl y t u rn s on t he stat ic drive s y st e m t o reduce current consumpt i o n t o t he minimu m level req u ire d f o r st at ic drive. t he on operat ion of t he st at ic drive s y st em in dicat e s t hat t h e nt 7502 is in st and b y m ode. t he int e r nal st at us in t he st and b y mode is as f o l l o w s : (1) st ops t he lcd po w e r s upp l y c i rcuit . (2) st ops t he lcd drive an d out pu t s t he v ss level as t he segment / common driver out put . ho w e ver, t he st at ic drive s y st em still oper ates. (3) holds t h e disp l a y d a t a an d op erat io n mode p r ovide d bef or e t he st art of t he st andb y mo de. (4) t he mpu can access t he bu il t - in displ a y ra m. w hen t he res e t command i s issued i n t he st andb y mo de, t he sleep mo d e is set . w hen t he lcd drive volt a ge le vel is given b y an e x t e rna l resi st iv e driver, t he current of t h is resist or must be cut so t hat it ma y be f i xe d t o f l oat ing or v ss level, prior to or concurrent l y w i t h t he sit uat ion of causin g t he n t 7502 t o ent er sleep mode or standby mode. w hen an e x t e r nal po w e r su pp l y is us ed, like w i s e, t he f unct i on of t h is ext e r nal po w e r su pp l y must be st op ped so t hat it ma y b e f i xed t o f l oat in g or v ss level, prior t o or concurre n t l y w i t h t he sit u at ion of caus in g t he nt 7502 t o ent er slee p mode or standby mode. 21. nop non-op erat io n command a0 e rd w r / wr d 7 d 6 d 5 d 4 d3 d2 d1 d0 0 1 0 1 1 1 0 0 0 1 1 22. t e st command t h is is t he de dicat e d i c chi p t e st comman d . i t must not be us ed f o r no rmal op erat i on. i f t he t e st co mmand is issu e d inadv ert ent l y , s e t t he res input t o lo w or issu e t h e reset comm and t o rel ease t he t e st mode. a0 e rd w r / wr d 7 d 6 d 5 d 4 d3 d2 d1 d0 0 1 0 1 1 1 1 * * * * *: in va lid bit caut io ns: t he n t 7502 maint a i n s an op e r at ion st at us sp ecif ied b y e a ch command. ho w e ver, t he int e r nal op erat io n st at us ma y b e chan g ed b y a hig h le vel of ambie n t noise. users m u st consider h o w t o sup p ress noise o n t he p a ckag e and s y st em or t o prevent am b i ent no ise i n se rt ion. t o pr event a spike i n n o ise, bu ilt -in s o f t w a re f o r peri o dical st at us ref r esh m ent is recom m end ed. t he t e st command c an be ins e rt ed i n a n u n e x p e ct ed pl ace. t heref ore it is r e commen d e d t o ent er t he t e st mode reset comman d f 0h duri ng t h e ref r esh seq u ence. 30
nt7502 code f u n c tio n command a0 rd wr d7 d6 d5 d4 d3 d2 d1 d0 (1) displ a y on / o f f 0 1 0 1 0 1 0 1 1 1 d t u rns on lcd pan el w h en g o e s high, a nd t u rns of f w h e n go es lo w (2) set displa y st art line 0 1 0 0 1 d ispl a y st art a ddress specifies ram display line for com0 (3) set page a ddress 0 1 0 1 0 1 1 p age a ddress set s t he displa y ram pag e in pag e address re gist er (4-1) set column addr ess 4 higher bit s 0 1 0 0 0 0 1 high er colum n addr ess set s 4 high er b i t s of column addr ess of disp la y ram in reg i st er (4-2) set column address 4 low e r b i ts 0 1 0 0 0 0 0 l o w e r co l u mn addr ess se ts 4 l o w e r bi ts o f co l u mn add re ss of displ a y ram in regist er (5) read st at u s 0 0 1 st at us 0 0 0 0 reads t h e st at us inf o rmat i o n (6) w r it e displ a y d a t a 1 1 0 w r it e dat a w r it es dat a in displ a y ram (7) read d i spl a y d a t a 1 0 1 read dat a reads dat a f r o m displa y ram (8) adc select 0 1 0 1 0 1 0 0 0 0 d set s t he displ a y ram ad dres s seg out put co rrespon de nce (9) normal/rev erse displ a y 0 1 0 1 0 1 0 0 1 1 d normal in dicat i on w h e n lo w , but f u ll i n d i ca ti on w h en h i gh (1 0 ) en tire disp lay on/off 0 1 0 1 0 1 0 0 1 0 0 1 select s norm a l displ a y ( 0 ) or ent i re displ a y on (1) (11) set lcd b i as 0 1 0 1 0 1 0 0 0 1 d s et s lcd driv e volt age b i as ra t i o (12) rea d -mo d i f y -w rit e 0 1 0 1 1 1 0 0 0 0 0 i n crement s co l u mn addr ess count er d u rin g each w r it e (13) e n d 0 1 0 1 1 1 0 1 1 1 0 rele ases t he read-m odif y - w rit e (14) reset 0 1 0 1 1 1 0 0 0 1 0 reset s int e r nal f unct i o n s (15) commo n out put mode se lect 0 1 0 1 1 0 0 d * * * selects com output scan d i re ct ion. * i n vali d dat a (16) set po w e r cont rol 0 1 0 0 0 1 0 1 operat io n st at us select s t he po w e r circuit op er at ion mode (17) v0 volt a g e regu lat o r in te rna l re sistor ra tio se t 0 1 0 0 0 1 0 0 resist or rat i o select int e r nal resist or rat i o (rb / ra) mode 0 1 0 1 0 0 0 0 0 0 1 set s t he v0 ou t put volt age elect r o n ic vol u me regist er (18) elect r o n ic volume mode set elect r onic v o lu me regist er s e t 0 1 0 * * elect r onic c ont rol valu e 0 1 0 1 0 1 0 1 1 0 d se ts sta t ic in d i ca to r on /off 0 : off 1 : o n (19) set st at ic indicat o r on /of f set st at ic indic a t o r regist er 0 1 0 * * * * * * m o d e set s t he f l ashi ng mod e (20) po w e r s a v e - - - - - - - - - - - compo u n d co mmand of dis p l a y of f and ent ire displa y on (21) n o p 0 1 0 1 1 1 0 0 0 1 1 comman d f o r non- oper at ion (22) t e st command 0 1 0 1 1 1 1 * * * * i c t e st command. do not us e ! (23) t e st mode reset 0 1 0 1 1 1 1 0 0 0 0 comman d of t e st mode reset not e : do not u s e an y ot her c o mmand, or s yst em malf unct i on ma y resu lt . 31
nt7502 comma nd des c r iption i n st ruct ion set up: ref e re nce 1. initializ ation not e : w i t h t h is i c , w h e n t he po w e r is a p p lie d, lcd drivi ng non-s e lect iv e p o t ent ia ls v2 an d v3 (seg pin ) and v1 an d v4 (com pin) are out put t h r oug h t he lc d driv in g out p u t pi ns s e g and com. w hen e l ect r ic charg e ermi ne s in t h e smoot hi n g capacit or con n e ct ing bet w e en t he l cd dr ivin g volt a ge out p u t pins (v 0 - v4) and t he v dd p i n, t he pict ure o n t he disp la y m a y inst ant a neo usl y b e come t o t a ll y d a rk w h en t h e po w e r is t u rn ed o n . t o avoid such f a i l ur e, w e recomm en d t he f o ll o w i ng f l o w sequ ence w h e n t u rnin g on t h e po w e r. 1. 1. w hen t he built -i n po w e r i s bein g used i mmediat e l y af t e r t u rnin g on t h e po w e r: when the power is stabilized initialized state (default) function setup by command input (user setup) (11) lcd bias setting (8) adc selection (15) common output state selection function setup by command input (user setup) (17) setting the built-in resistance radio for regulation of the v 0 voltage (18) electronic volume control function setup by command input (user setup) (16) power control setting this concludes the initialization arrange to execute all the procedures from releasing the reset state through setting the power control within 5ms release the reset state. (res pin = "h") turn on the v dd -v ss power keeping the res pin = "l" t he target time of 5ms w ill var y d epe ndi n g on the pan el characteristics and capac itan ce of the smoothin g capacit or. t heref ore, w e sugg est y o u t o cond uct an op erat io n check u s ing t he act u al equi pme n t . 32
nt7502 1. 2. w hen t he built -i n po w e r i s not bein g use d immedi at el y af t e r t u rning o n t he po w e r when the power is stabilized initialized state (default) function setup by command input (user setup) (11) lcd bias setting (8) adc selection (15) common output state selection function setup by command input (user setup) (17) setting the built-in resistance radio for regulation of the v 0 voltage (18) electronic volume control power saver off function setup by command input (user setup) (16) power control setting this concludes the initialization power saver start (multiple commands) turn on the v dd - v ss power keeping the res pin = "l" release the reset state. (res pin = "h") arrange to start the power saver within 5ms after releasing the reset statue. arrange to start power control setting within 5ms after turning off the power saver t he t a rget t i me of 5ms w i l l vary de pen din g o n t he pane l charact e rist ics an d t he capacit a n ce of t he smoot hin g capacit o r . t heref ore, w e sugg est y o u t o cond uct an op erat io n check u s ing t he act u al equi pme n t . 33
nt7502 1 . da ta display end of initialization function setup by command input (user setup) (2) display start line set (3) page address set (4) column address set function setup by command input (user setup) (6) display data write function setup by command input (user setup) (1) display on/off end of data display 2 . po w e r off optional status function setup by command input (user setup) (20) power save v dd -v ss power off t he t a rget t i me of 5ms w i l l var y de pe ndi ng o n t he pan el ch aract e rist ics a n d capac it ance of t he smoot hi ng cap a cit o r. t heref ore, w e sugg est y o u t o cond uct an op erat io n check u s ing t he act u al equi pme n t . 34
nt7502 absolu te ma ximum ratin g * dc sup p l y volt age (v dd, v dd2 ) .................... .-0 . 3 v to +3 .6 v dc sup p l y volt age (v out ) .............................. -0 .3 v to +1 2 v dc sup p l y volt age (v 0 ) ................................ -0 .3 v to +1 1 . 5 v input voltage .......................................... -0.3v to v dd + 0. 3v op e r a t ing ambie n t t e mp e r a t ure ................... -4 0 c to +8 5 c storage t e mper ature .................................. -55 c to +1 2 5 c *c omment s st resses abov e t hose list e d under "a bso l ut e ma ximum rat i ngs " ma y cause perma nent dama ge t o t h is device. t hese are st ress rat i ngs on l y . f unct i onal o perat i on of t h i s device u nder t hese or an y o t her condit i ons above t hose indic a t ed i n t he operat i o n a l s e ct ions of t h is specif icat i on is not impl ie d or i n t end ed. e x p o s ure t o t he abs olut e m a ximum rat i ng c ond it io ns f o r e x t e n d ed p e rio d s m a y af f e ct devi c e relia bil i t y . electrical ch arac teris t ics dc chara c teri stics (v ss = 0 v , v dd = 2. 7 - 3. 3v t a = -40 t o 85 c un less ot her w i s e spec if ied) sy m b o l m i n . ty p. ma x . unit conditi o n v dd operat in g volt a g e 2. 4 3 . 5 v 2. 4 3 . 5 v v dd2 o p e r a t in g volt a g e 2. 4 3 . 0 v quadru p le b o o s t i n g v out boost e r out p u t volt ag e 6. 0 12. 0 v v 0 volt ag e regu lat o r oper at ion vo lt a ge 4. 5 11. 5 v v reg1 r e f e re nce volt a g e 2. 0 4 2. 10 2. 1 6 v t a = 2 5 c, -0. 05%/ c v reg2 r e f e re nce volt a g e 2. 0 0 2. 10 2. 2 0 v t a = 2 5 c, -0. 2%/ c i dd1 d y namic curr e n t consum pt ion 1 - 2 1 3 5 a v dd = 3 v , v 0 = 11v, built -i n p o w e r su ppl y of f , displ a y on, dis p la y d a t a = checker and n o ac cess, t a = 2 5 c i dd2 d y namic curr e n t consum pt ion 2 - 9 6 1 6 0 a 4x boost i ng, v dd , v dd2 = 3 v , v 0 = 11v, built -in po w e r s upp l y o n , displ a y on, d i spla y d a t a = checker and n o access, t a = 2 5 c, t e mperat ur e gra d ient is -0. 05%/ c, w h en v0 volt a ge i n t e rna l resist or is used. norm al mode i dd3 d y namic curr e n t consum pt ion 3 - 1 5 3 2 5 5 a 4x boost i ng, v dd, v dd2 = 3 v , v 0 = 11v, built -in po w e r s upp l y o n , displ a y on, d i spla y d a t a = checker and n o access, t a = 2 5 c, t e mperat ur e gra d ient is -0. 05%/ c, w h en v0 volt a ge i n t e rna l resist or is used. hi gh po w e r mode i sp slee p mode c u rrent consum pt ion 0 . 01 5 a d urin g slee p, t a = 2 5 c i sb st andb y mod e current consum pt ion 4 8 a d urin g st and b y , t a = 2 5 c v ih c high- leve l inp u t volt age 0. 8 x v dd v dd v v il c lo w - l e vel i n p u t volt age v ss 0. 2 x v dd v a0 , d0 - d7 , rd (e), wr ( w / r ), 1 cs , cs2 , cls, cl, fr, m/s, c86, p/s, dof , res , t m ps, vrs, i r s, and hpm v ohc high- leve l out p u t volt age 0. 8 x v dd v dd v i oh = -0 .5 ma ( d 0 - d7 , fr, f r s, dof , and cl) v olc lo w -lev el o u t p ut volt age v ss 0. 2 x v dd i ol = 0. 5ma (d0 - d7, f r , f r s, dof , and cl) i li i nput leak ag e current -1. 0 1. 0 a v in = v dd or v ss (a0, rd (e), wr ( w / r ), 1 cs , cs2, cls, m/ s, c86, p/ s, i r s, t m ps, vrs and res ) i hz hz leaka ge cur r ent -3. 0 3. 0 a w hen t he d0 - d7, f r , cl, and dof are in hi gh imped anc e p a rame t e r 35
nt7502 dc chara c teri stics (co n t i nu ed) sy m b o l p a rame t e r m i n . ty p. ma x . unit conditi o n r on1 lcd driv er on resist ance 2. 0 3 . 5 k ? v 0 = 11. 0v r on2 lcd driv er on resist ance 3. 2 5 . 4 k ? v 0 = 8. 0v t a = 2 5 c, t h e s e are t he resi st ance values f o r w h e n a 0. 1v volt a g e is app lie d bet w e en t he o u t put t e rmina l segn or comn and t he various po w e r suppl y te rmin a l s (v1 , v2 , v3 , v4 ). c in i nput pad c apa cit y 5. 0 8 . 0 pf t a = 2 5 c, f = 1mhz f osc o s c i l l a t i o n freq uenc y 2 7 33 3 9 khz t a = 2 5 c no te s: 1 . volt a ges v 0 R v 1 R v 2 R v 3 R v 4 R v ss must alw a ys be sat i sf i ed. 36
nt7502 ac char ac te ristics (1) syste m b u ses read / w r ite ch ara c teristic s 1 (f o r th e 8080 serie s mpu) t as8 t ah8 t cyc8 t cclw t cclr t cchw t cchr t ds8 t dh8 t acc8 t ch8 a0 d0 - d7 (write) d0 - d7 (read) rd , wr 1 cs (cs2 = "1") (v dd = 2. 7 - 3.3v, t a = -40 - 85 sy m b o l p a rame t e r min. ty p. ma x . unit conditi o n t ah 8 address h o ld t i me 0 ns t as 8 address set u p t i me 0 ns t cyc8 s y st em c y cle t i me 300 ns t cclw cont rol l puls e w i dt h (w r) 90 ns t cclr cont rol l puls e w i dt h (rd) 120 ns t cchw cont rol h p u ls e w i dt h (w r) 120 ns t cchr cont rol h p u ls e w i dt h (rd) 60 ns t ds8 dat a set up t i m e 40 ns t dh8 dat a ho ld t i me 15 ns t a cc8 rd access time 1 4 0 n s c l = 100pf t ch8 o u t put disab l e t i m e 1 0 1 0 0 n s c l = 100pf *1. t he inp u t si gnal rise t i m e a nd f a l l t i me (t r , t f ) is specif i ed at 15ns or l e ss. w hen t h e s y st e m c y cl e t i me is ext r em el y f a st , (t r +t f ) ? cyc8 -t cclw -t cchw ) for (t r +t f ) ? cyc8 -t cclr -t cchr ) are sp ecif ied. *2. all t i ming is specif ie d usin g 20% a nd 8 0 % of v dd as t he ref e renc e. *3. t cclw an d t cclr are sp ecif ied as t h e over l ap b e t w e en 1 cs being ?l? (cs 2 = ?h?) and wr and rd bein g at t h e ?l? leve l. 37
nt7502 system buse s re ad/write cha r a c teri stics 2 (6 800 se ries mpu) t as6 t ah6 t cyc6 t ds6 t dh6 t acc6 t oh6 a0 d0 - d7 (write) d0 - d7 (read) 1 cs (cs2 = "1") e w / r t ewhw t ewhr t ewlw t ewlr (v dd = 2. 7 - 3.3v, t a = -40 - 85 c) sy m b o l p a rame t e r m i n . ty p . ma x . unit conditi o n t cyc6 s y st em c y cle t i me 300 ns t as 6 address set u p t i me 0 ns t ah 6 address h o ld t i me 0 ns t ds6 dat a set up t i m e 40 ns t dh6 dat a ho ld t i me 15 ns t oh6 o u t put disab l e t i m e 1 0 1 0 0 n s c l = 100pf t a cc6 a c c e s s t i m e 1 4 0 n s c l = 100pf t ewhr enab le h pu lse w i dt h (rea d) 120 ns t ewhw enab le h pu lse w i dt h (w rit e ) 90 ns t ewlr enab le l p u lse w i dt h (rea d) 60 ns t ewlw enab le l p u lse w i dt h (w rit e ) 120 ns *1. t he inp u t si gnal rise t i m e a nd f a l l t i me (t r , t f ) is specif i ed at 15ns or l e ss. w hen t h e s y st e m c y cl e t i me is ext r em el y f a st , (t r +t f ) (t cyc6 -t ewlw -t ewhw ) for (t r +t f ) (t cyc6 -t ewlr -t ewhr ) are specif ie d. *2. all t i mings are specif i ed u s ing 2 0 % an d 80% of v dd as t he ref e renc e. *3. t ewlw and t ewlr are spec i f ied as t he ov e r lap b e t w ee n 1 cs bein g ?l? (cs2 = ?h?) and e. 38
nt7502 (2) serial interface t sas t sah t sd s t sdh t css t csh t scyc t slw t shw tr tf a0 1 cs (cs2 = "1") scl si (v dd = 2. 7 - 3.3v, t a = -40 - 85 sy m b o l p a rame t e r m i n . ty p. ma x . unit conditi o n t scyc serial cl ock c y cle 250 ns t shw serial cl ock h pulse w i dt h 100 ns t slw serial cl ock l p u lse w i dt h 100 ns t sa s address set u p t i me 150 ns t sa h address h o ld t i me 150 ns t sds dat a set up t i m e 100 ns t sdh dat a ho ld t i me 100 ns t css cs serial clock time 1 5 0 n s t csh cs serial clock time 1 5 0 n s *1. t he input signal ris e t i me a nd f a ll t i me (t r , t f ) are specif ied at 15ns or less *2. all t i mings are specif i ed u s ing 2 0 % an d 80% of v dd as t he st andar d. 39
nt7502 (3 ) dis p lay control t i ming cl (out) t dfr fr (v dd = 2. 7 - 3.3v, t a = -40 - 85 sy m b o l p a rame t e r m i n . ty p. ma x . unit conditi o n t dfr f r dela y t i me 20 80 ns c l = 50pf (4) reset t i min g t rw internal circuit status res t r during reset end of reset (v dd = 2. 7 - 3.3v, t a = -40 - 85 sy m b o l p a rame t e r m i n . ty p. ma x . unit conditi o n t r r e se t time 1 . 0 rw reset lo w puls e w i dt h 1. 0 40
nt7502 microproc es sor inter f ac e (for re fer e n ce only ) 808 0-se ries m i cro p r o cesso r s v cc a0 a1 to a7 d0 to d7 gnd iorq wr res rd a0 d0 to d7 wr res rd 1 cs v ss c86 p/s decoder reset v ss v ss v dd mpu nt7502 v dd v dd cs2 figure . 8 680 0-se ries m i cro p r o cesso r s v cc a0 a1 to a15 d0 to d7 gnd a0 d0 to d7 2 cs w / r res e 1 cs v ss c86 p/s decoder reset v ss v dd mpu nt7502 v dd v dd vma w / r res e v dd figure . 9 41
nt7502 conn ection s bet w e e n lcd driv ers (fo r refer e nc e only ) t he liquid cr yst a l disp la y ar ea can be e n lar g e d w i t h eas e t h roug h t he use of mult iple nt 75 02 chi p s. use same eq uipm en t t y p e . nt 750 2 (mast er) ! nt 7502 (sla v e ) v dd output v ss nt7502 master m/s input m/s fr fr cl cl dof dof nt7502 slave res res r r v dd 42
nt7502 bonding dia g ram 11032 u m 1150 um 101 117 118 282 281 298 nt7502 100 1 dummy dummy dummy0 dummy4 dummy5 dummy11 alk_l alk_r ( 0 , 0 ) x y pad no. de s i gna tion x y pad no. de s i gna tion x y 1 n c -454 8. 6 5 -497. 5 3 1 v dd - 1 8 4 8. 6 5 -497. 5 2 f r s -445 8. 6 5 -497. 5 3 2 v dd - 1 7 5 8. 6 5 -497. 5 3 f r -436 8. 6 5 -497. 5 3 3 v dd - 1 6 6 8. 6 5 -497. 5 4 c l -427 8. 6 5 -497. 5 3 4 v dd2 - 1 5 7 8. 6 5 -497. 5 5 dof -418 8. 6 5 - 4 9 7 . 5 3 5 v dd2 - 1 4 8 8. 6 5 -497. 5 6 n c -409 8. 6 5 -497. 5 3 6 v dd2 - 1 3 9 8. 6 5 -497. 5 7 v ss - 4 0 0 8. 6 5 -497. 5 3 7 v ss - 1 3 0 8. 6 5 -497. 5 8 1 cs -391 8. 6 5 - 4 9 7 . 5 3 8 v ss - 1 2 1 8. 6 5 -497. 5 9 c s 2 -382 8. 6 5 -497. 5 3 9 v ss - 1 1 2 8. 6 5 -497. 5 1 0 v dd - 3 7 3 8. 6 5 -497. 5 4 0 v ss - 1 0 3 8. 6 5 -497. 5 11 res -364 8. 6 5 - 4 9 7 . 5 4 1 vout -948. 6 5 -497. 5 1 2 a 0 -355 8. 6 5 -497. 5 4 2 vout -858. 6 5 -497. 5 1 3 v ss - 3 4 6 8. 6 5 -497. 5 4 3 cap3+ -768. 6 5 -497. 5 14 wr -337 8. 6 5 - 4 9 7 . 5 4 4 cap3+ -678. 6 5 -497. 5 15 rd -328 8. 6 5 - 4 9 7 . 5 4 5 c a p 1 - - 5 8 8 . 6 5 -497. 5 1 6 v dd -319 8. 6 5 - 4 9 7 . 5 4 6 c a p 1 - - 4 9 8 . 6 5 -497. 5 1 7 d 0 -310 8. 6 5 -497. 5 4 7 cap1+ -408. 6 5 -497. 5 1 8 d 1 -301 8. 6 5 -497. 5 4 8 cap1+ -318. 6 5 -497. 5 1 9 d 2 -292 8. 6 5 -497. 5 4 9 cap2+ -228. 6 5 -497. 5 2 0 d 3 -283 8. 6 5 -497. 5 5 0 cap2+ -138. 6 5 -497. 5 2 1 d 4 -274 8. 6 5 -497. 5 5 1 c a p 2 - -48. 6 5 -497. 5 2 2 d 5 -265 8. 6 5 -497. 5 5 2 c a p 2 - 41. 3 5 -497. 5 2 3 d 6 -256 8. 6 5 -497. 5 5 3 v dd 1 3 1 . 3 5 -497. 5 2 4 d 7 -247 8. 6 5 -497. 5 5 4 vext 221. 3 5 -497. 5 2 5 v ss - 2 3 8 8. 6 5 -497. 5 5 5 v r s 311. 3 5 -497. 5 2 6 v dd - 2 2 9 8. 6 5 -497. 5 5 6 v ss 4 0 1 . 3 5 -497. 5 2 7 d u t y 0 -220 8. 6 5 -497. 5 5 7 v 1 491. 3 5 -497. 5 2 8 d u t y 1 -211 8. 6 5 -497. 5 5 8 v 1 581. 3 5 -497. 5 2 9 v ss - 2 0 2 8. 6 5 -497. 5 5 9 v 2 671. 3 5 -497. 5 3 0 v dd - 1 9 3 8. 6 5 -497. 5 6 0 v 2 761. 3 5 -497. 5 43
nt7502 bonding dia g ram (c ontin ue d) pad no. de s i gna tion x y pad no. de s i gna tion x y 6 1 v 3 851. 3 5 -497. 5 1 0 1 c o m 3 1 545 3 -525. 6 6 2 v 3 941. 3 5 -497. 5 1 0 2 c o m 3 0 545 3 -454. 6 6 3 v 4 103 1. 3 5 -497. 5 1 0 3 c o m 2 9 545 3 -389. 6 6 4 v 4 112 1. 3 5 -497. 5 1 0 4 c o m 2 8 545 3 -324. 6 6 5 v 0 121 1. 3 5 -497. 5 1 0 5 c o m 2 7 545 3 -259. 6 6 6 v 0 130 1. 3 5 -497. 5 1 0 6 c o m 2 6 545 3 -194. 6 6 7 v r 139 1. 3 5 -497. 5 1 0 7 c o m 2 5 545 3 -129. 6 6 8 v r 148 1. 3 5 -497. 5 1 0 8 c o m 2 4 545 3 -64. 6 6 9 v ss 1 5 7 1. 3 5 -497. 5 1 0 9 c o m 2 3 545 3 0. 4 7 0 v ss 1 6 6 1. 3 5 -497. 5 1 1 0 c o m 2 2 545 3 65. 4 7 1 v dd 1 7 5 1. 3 5 -497. 5 1 1 1 c o m 2 1 545 3 130. 4 7 2 m / s 184 1. 3 5 -497. 5 1 1 2 c o m 2 0 545 3 195. 4 7 3 c l s 193 1. 3 5 -497. 5 1 1 3 c o m 1 9 545 3 260. 4 7 4 v ss 2 0 2 1. 3 5 -497. 5 1 1 4 c o m 1 8 545 3 325. 4 7 5 c 8 6 211 1. 3 5 -497. 5 1 1 5 c o m 1 7 545 3 390. 4 7 6 p / s 220 1. 3 5 -497. 5 1 1 6 c o m 1 6 545 3 455. 4 7 7 v dd 2 2 9 1. 3 5 -497. 5 1 1 7 c o m 1 5 545 3 526. 4 78 hpm 238 1. 3 5 - 4 9 7 . 5 1 1 8 c o m 1 4 530 3. 5 504. 4 5 7 9 v ss 2 4 7 1. 3 5 -497. 5 1 1 9 c o m 1 3 523 2. 5 504. 4 5 8 0 i r s 256 1. 3 5 -497. 5 1 2 0 c o m 1 2 516 7. 5 504. 4 5 8 1 v dd 2 6 5 1. 3 5 -497. 5 1 2 1 c o m 1 1 510 2. 5 504. 4 5 8 2 t m p s 274 1. 3 5 -497. 5 1 2 2 c o m 1 0 503 7. 5 504. 4 5 8 3 v ss 2 8 3 1. 3 5 -497. 5 1 2 3 c o m 9 497 2. 5 504. 4 5 8 4 n c 292 1. 3 5 -497. 5 1 2 4 c o m 8 490 7. 5 504. 4 5 8 5 n c 301 1. 3 5 -497. 5 1 2 5 c o m 7 484 2. 5 504. 4 5 8 6 n c 310 1. 3 5 -497. 5 1 2 6 c o m 6 477 7. 5 504. 4 5 8 7 n c 319 1. 3 5 -497. 5 1 2 7 c o m 5 471 2. 5 504. 4 5 8 8 n c 328 1. 3 5 -497. 5 1 2 8 c o m 4 464 7. 5 504. 4 5 8 9 n c 337 1. 3 5 -497. 5 1 2 9 c o m 3 458 2. 5 504. 4 5 9 0 t e st 3 346 1. 3 5 -497. 5 1 3 0 c o m 2 451 7. 5 504. 4 5 9 1 v dd 3 5 5 1. 3 5 -497. 5 1 3 1 c o m 1 445 2. 5 504. 4 5 9 2 n c 364 1. 3 5 -497. 5 1 3 2 c o m 0 438 7. 5 504. 4 5 9 3 n c 373 1. 3 5 -497. 5 1 3 3 c o m s 432 2. 5 504. 4 5 9 4 n c 382 1. 3 5 -497. 5 1 3 4 s e g 0 425 7. 5 504. 4 5 9 5 n c 391 1. 3 5 -497. 5 1 3 5 s e g 1 419 2. 5 504. 4 5 9 6 n c 400 1. 3 5 -497. 5 1 3 6 s e g 2 412 7. 5 504. 4 5 9 7 n c 409 1. 3 5 -497. 5 1 3 7 s e g 3 406 2. 5 504. 4 5 9 8 n c 418 1. 3 5 -497. 5 1 3 9 s e g 4 399 7. 5 504. 4 5 9 9 n c 427 1. 3 5 -497. 5 1 3 9 s e g 5 393 2. 5 504. 4 5 1 0 0 n c 436 1. 3 5 -497. 5 1 4 0 s e g 6 386 7. 5 504. 4 5 44
nt7502 bonding dia g ram (c ontin ue d) pad no. de s i gna tion x y pad no. de s i gna tion x y 1 4 1 s e g 7 380 2. 5 504. 4 5 1 8 1 s e g 4 7 120 2. 5 504. 4 5 1 4 2 s e g 8 373 7. 5 504. 4 5 1 8 2 s e g 4 8 113 7. 5 504. 4 5 1 4 3 s e g 9 367 2. 5 504. 4 5 1 8 3 s e g 4 9 107 2. 5 504. 4 5 1 4 4 s e g 1 0 360 7. 5 504. 4 5 1 8 4 s e g 5 0 100 7. 5 504. 4 5 1 4 5 s e g 1 1 354 2. 5 504. 4 5 1 8 5 s e g 5 1 942. 5 504. 4 5 1 4 6 s e g 1 2 347 7. 5 504. 4 5 1 8 6 s e g 5 2 877. 5 504. 4 5 1 4 7 s e g 1 3 341 2. 5 504. 4 5 1 8 7 s e g 5 3 812. 5 504. 4 5 1 4 8 s e g 1 4 334 7. 5 504. 4 5 1 8 8 s e g 5 4 747. 5 504. 4 5 1 4 9 s e g 1 5 328 2. 5 504. 4 5 1 8 9 s e g 5 5 682. 5 504. 4 5 1 5 0 s e g 1 6 321 7. 5 504. 4 5 1 9 0 s e g 5 6 617. 5 504. 4 5 1 5 1 s e g 1 7 315 2. 5 504. 4 5 1 9 1 s e g 5 7 552. 5 504. 4 5 1 5 2 s e g 1 8 308 7. 5 504. 4 5 1 9 2 s e g 5 8 487. 5 504. 4 5 1 5 3 s e g 1 9 302 2. 5 504. 4 5 1 9 3 s e g 5 9 422. 5 504. 4 5 1 5 4 s e g 2 0 295 7. 5 504. 4 5 1 9 4 s e g 6 0 357. 5 504. 4 5 1 5 5 s e g 2 1 289 2. 5 504. 4 5 1 9 5 s e g 6 1 292. 5 504. 4 5 1 5 6 s e g 2 2 282 7. 5 504. 4 5 1 9 6 s e g 6 2 227. 5 504. 4 5 1 5 7 s e g 2 3 276 2. 5 504. 4 5 1 9 7 s e g 6 3 162. 5 504. 4 5 1 5 8 s e g 2 4 269 7. 5 504. 4 5 1 9 8 s e g 6 4 97. 5 504. 4 5 1 5 9 s e g 2 5 263 2. 5 504. 4 5 1 9 9 s e g 6 5 32. 5 504. 4 5 1 6 0 s e g 2 6 256 7. 5 504. 4 5 2 0 0 s e g 6 6 -32. 5 504. 4 5 1 6 1 s e g 2 7 250 2. 5 504. 4 5 2 0 1 s e g 6 7 -97. 5 504. 4 5 1 6 2 s e g 2 8 243 7. 5 504. 4 5 2 0 2 s e g 6 8 -162. 5 504. 4 5 1 6 3 s e g 2 9 237 2. 5 504. 4 5 2 0 3 s e g 6 9 -227. 5 504. 4 5 1 6 4 s e g 3 0 230 7. 5 504. 4 5 2 0 4 s e g 7 0 -292. 5 504. 4 5 1 6 5 s e g 3 1 224 2. 5 504. 4 5 2 0 5 s e g 7 1 -357. 5 504. 4 5 1 6 6 s e g 3 2 217 7. 5 504. 4 5 2 0 6 s e g 7 2 -422. 5 504. 4 5 1 6 7 s e g 3 3 211 2. 5 504. 4 5 2 0 7 s e g 7 3 -487. 5 504. 4 5 1 6 8 s e g 3 4 204 7. 5 504. 4 5 2 0 8 s e g 7 4 -552. 5 504. 4 5 1 6 9 s e g 3 5 198 2. 5 504. 4 5 2 0 9 s e g 7 5 -617. 5 504. 4 5 1 7 0 s e g 3 6 191 7. 5 504. 4 5 2 1 0 s e g 7 6 -682. 5 504. 4 5 1 7 1 s e g 3 7 185 2. 5 504. 4 5 2 1 1 s e g 7 7 -747. 5 504. 4 5 1 7 2 s e g 3 8 178 7. 5 504. 4 5 2 1 2 s e g 7 8 -812. 5 504. 4 5 1 7 3 s e g 3 9 172 2. 5 504. 4 5 2 1 3 s e g 7 9 -877. 5 504. 4 5 1 7 4 s e g 4 0 165 7. 5 504. 4 5 2 1 4 s e g 8 0 -942. 5 504. 4 5 1 7 5 s e g 4 1 159 2. 5 504. 4 5 2 1 5 s e g 8 1 -100 7. 5 504. 4 5 1 7 6 s e g 4 2 152 7. 5 504. 4 5 2 1 6 s e g 8 2 -107 2. 5 504. 4 5 1 7 7 s e g 4 3 146 2. 5 504. 4 5 2 1 7 s e g 8 3 -113 7. 5 504. 4 5 1 7 8 s e g 4 4 139 7. 5 504. 4 5 2 1 8 s e g 8 4 -120 2. 5 504. 4 5 1 7 9 s e g 4 5 133 2. 5 504. 4 5 2 1 9 s e g 8 5 -126 7. 5 504. 4 5 1 8 0 s e g 4 6 126 7. 5 504. 4 5 2 2 0 s e g 8 6 -133 2. 5 504. 4 5 45
nt7502 bonding dia g ram (c ontin ue d) pad no. de s i gna tion x y pad no. de s i gna tion x y 2 2 1 s e g 8 7 -139 7. 5 504. 4 5 2 6 1 s e g 1 2 7 -399 7. 5 504. 4 5 2 2 2 s e g 8 8 -146 2. 5 504. 4 5 2 6 2 s e g 1 2 8 -406 2. 5 504. 4 5 2 2 3 s e g 8 9 -152 7. 5 504. 4 5 2 6 3 s e g 1 2 9 -412 7. 5 504. 4 5 2 2 4 s e g 9 0 -159 2. 5 504. 4 5 2 6 4 s e g 1 3 0 -419 2. 5 504. 4 5 2 2 5 s e g 9 1 -165 7. 5 504. 4 5 2 6 5 s e g 1 3 1 -425 7. 5 504. 4 5 2 2 6 s e g 9 2 -172 2. 5 504. 4 5 2 6 6 c o m 3 2 -432 2. 5 504. 4 5 2 2 7 s e g 9 3 -178 7. 5 504. 4 5 2 6 7 c o m 3 3 -438 7. 5 504. 4 5 2 2 8 s e g 9 4 -185 2. 5 504. 4 5 2 6 8 c o m 3 4 -445 2. 5 504. 4 5 2 2 9 s e g 9 5 -191 7. 5 504. 4 5 2 6 9 c o m 3 5 -451 7. 5 504. 4 5 2 3 0 s e g 9 6 -198 2. 5 504. 4 5 2 7 0 c o m 3 6 -458 2. 5 504. 4 5 2 3 1 s e g 9 7 -204 7. 5 504. 4 5 2 7 1 c o m 3 7 -464 7. 5 504. 4 5 2 3 2 s e g 9 8 -211 2. 5 504. 4 5 2 7 2 c o m 3 8 -471 2. 5 504. 4 5 2 3 3 s e g 9 9 -217 7. 5 504. 4 5 2 7 3 c o m 3 9 -477 7. 5 504. 4 5 2 3 4 s e g 1 0 0 -224 2. 5 504. 4 5 2 7 4 c o m 4 0 -484 2. 5 504. 4 5 2 3 5 s e g 1 0 1 -230 7. 5 504. 4 5 2 7 5 c o m 4 1 -490 7. 5 504. 4 5 2 3 6 s e g 1 0 2 -237 2. 5 504. 4 5 2 7 6 c o m 4 2 -497 2. 5 504. 4 5 2 3 7 s e g 1 0 3 -243 7. 5 504. 4 5 2 7 7 c o m 4 3 -503 7. 5 504. 4 5 2 3 8 s e g 1 0 4 -250 2. 5 504. 4 5 2 7 8 c o m 4 4 -510 2. 5 504. 4 5 2 3 9 s e g 1 0 5 -256 7. 5 504. 4 5 2 7 9 c o m 4 5 -516 7. 5 504. 4 5 2 4 0 s e g 1 0 6 -263 2. 5 504. 4 5 2 8 0 c o m 4 6 -523 2. 5 504. 4 5 2 4 1 s e g 1 0 7 -269 7. 5 504. 4 5 2 8 1 c o m 4 7 -530 3. 5 504. 4 5 2 4 2 s e g 1 0 8 -276 2. 5 504. 4 5 2 8 2 c o m 4 8 -545 3 526. 4 2 4 3 s e g 1 0 9 -282 7. 5 504. 4 5 2 8 3 c o m 4 9 -545 3 455. 4 2 4 4 s e g 1 1 0 -289 2. 5 504. 4 5 2 8 4 c o m 5 0 -545 3 390. 4 2 4 5 s e g 1 1 1 -295 7. 5 504. 4 5 2 8 5 c o m 5 1 -545 3 325. 4 2 4 6 s e g 1 1 2 -302 2. 5 504. 4 5 2 8 6 c o m 5 2 -545 3 260. 4 2 4 7 s e g 1 1 3 -308 7. 5 504. 4 5 2 8 7 c o m 5 3 -545 3 195. 4 2 4 8 s e g 1 1 4 -315 2. 5 504. 4 5 2 8 8 c o m 5 4 -545 3 130. 4 2 4 9 s e g 1 1 5 -321 7. 5 504. 4 5 2 8 9 c o m 5 5 -545 3 65. 4 2 5 0 s e g 1 1 6 -328 2. 5 504. 4 5 2 9 0 c o m 5 6 -545 3 0. 4 2 5 1 s e g 1 1 7 -334 7. 5 504. 4 5 2 9 1 c o m 5 7 -545 3 -64. 6 2 5 2 s e g 1 1 8 -341 2. 5 504. 4 5 2 9 2 c o m 5 8 -545 3 -129. 6 2 5 3 s e g 1 1 9 -347 7. 5 504. 4 5 2 9 3 c o m 5 9 -545 3 -194. 6 2 5 4 s e g 1 2 0 -354 2. 5 504. 4 5 2 9 4 c o m 6 0 -545 3 -259. 6 2 5 5 s e g 1 2 1 -360 7. 5 504. 4 5 2 9 5 c o m 6 1 -545 3 -324. 6 2 5 6 s e g 1 2 2 -367 2. 5 504. 4 5 2 9 6 c o m 6 2 -545 3 -389. 6 2 5 7 s e g 1 2 3 -373 7. 5 504. 4 5 2 9 7 c o m 6 3 -545 3 -454. 6 2 5 8 s e g 1 2 4 -380 2. 5 504. 4 5 2 9 8 c o m s -545 3 -525. 6 2 5 9 s e g 1 2 5 -386 7. 5 504. 4 5 a l k _ l 514 0 2 0 0 2 6 0 s e g 1 2 6 -393 2. 5 504. 4 5 a l k _ r -514 0 2 0 0 46
nt7502 dummy pad loca t ion (to t al: 12 pin ) n o x y n o x y no x y n o x y 0 - 5 0 6 0 -497. 5 0 3 - 4 7 9 0 -497. 5 0 6 455 0 -497. 5 0 9 482 0 -497. 5 0 1 - 4 9 7 0 -497. 5 0 4 - 4 7 0 0 -497. 5 0 7 464 0 -497. 5 0 1 0 491 0 -497. 5 0 2 - 4 8 8 0 -497. 5 0 5 4 4 6 0 -497. 5 0 8 473 0 - 4 9 7 . 5 0 1 1 5 0 0 0 -497. 5 0 47
nt7502 packag e information nt7502 a1 a2 a1 a2 b1 b4 d1 c2 d3 d3 c3 b2 b3 162m1n d1 h r c1 d3 c4 d3 d1 h r c1 d3 c4 d3 101m1n 15nm1 n 15nm1 n m1 d2 d2 d2 d2 n m1 n m2 4m2n n m2 6m2n n m4 n m4 n j m3 m3 j m3 m3 m3 m3 m1 m1 chip outline dimensions unit : sy mbol dime ns ions in m sy mbol dime ns ions in m a 1 2 1 2 . 5 d 2 9 0 a 2 6 3 d 3 7 1 b 1 4 5 6 r 3 5 b 2 1 5 1 . 3 5 h 304. 4 5 b 3 9 8 . 6 5 j 3 1 3 b 4 5 1 6 m 1 4 2 c 1 4 8 . 6 m 2 4 6 c 2 7 0 . 5 5 m 3 5 6 c 3 7 7 . 5 m 4 5 8 c 4 4 9 . 4 n 9 0 d 1 6 5 48
nt7502 tab pin la y out nt7502h-tabf1 v4 cs1 cs2 res a0 wr rd d0 d1 d2 d3 d4 d5 d6 d7 duty0 duty1 vdd vdd2 vss vout nc cap3+ cap1- cap2+ cap2- vext vrs v1 v2 v3 nc v0 vr m/s cls c86 p/s hpm nc nc nc nc fr cl dof nc irs cap1+ 40 41 42 43 44 45 46 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 47 243 244 245 246 247 com62 com63 coms frs fr 211 212 213 214 215 seg130 seg131 com32 com33 com34 78 79 80 81 82 83 com1 com0 coms seg0 seg1 seg2 49 50 51 48 com31 com30 com29 com28 (coppe r side vie w ) 49
nt7502 50 external view of tab pins
nt7502 ca utions con c e r ning stora g e : 1. w hen st orin g t he pro duct , it is recommen ded t o leave it in it s shippi ng p a c k age. af t e r t he seal o f t he packing b ag is remov ed , st ore t he prod uct s in a nit r og en at mosp here . 2. st orage co ndit i ons are g i ven belo w : stora g e s t a t e stora g e c ondi tions not open ed (less th an 90 d a y s ) t e mperat ure: 5 t o 30 (less th an 30 d a y s ) room t e mp era t ure, dr y n i t r og en at mosp here 3. don' t st ore t he pro duct in a locat i o n e x pos ed t o corrosiv e gas or e x cessi ve dust . 4. don' t st ore t he pro duct in a locat i o n e x pos ed t o direct su nlig ht of subjec t t o sharp chan ges in t e mp era t ure. 5. don' t st ore t he pro duct suc h t hat it is subj ect ed t o an e x c e ssive lo ad w e i ght , such as st acking. 6. det e rior at io n of t he plat i n g ma y occ u r af t e r lon g -t erm st orag e, so speci a l care is re qui red. i t is recommended t o ins pect t he pro duct s be f o re use. 51
nt7502 tra y informa t i o n a e f w2 w1 t1 t2 section x-x b xx yy 5*33 h g e f t1 t2 w2 section y-y c h g w1 d tra y outline dimensions unit: mm sy mbol dime ns ions in mm sy mbol dime ns ions in mm a 1 . 4 0 g 0. 8 4 b 2 . 0 0 h 4. 2 0 c 1 1 . 2 8 w 1 76. 0 d 1 1 . 8 8 w 2 68. 0 e 1 . 6 0 t 1 71. 0 f 1 . 4 0 t 2 68. 3 52
nt7502 ordering information part no . pack ag e nt 7502h-bdt gold bum p on chip t r a y nt 7502h-t abf 1 t a b f o r m 53
nt7502 54 data sheet version history version content date 1.0 cu foil changed from 1/2oz to 25m.(page50 & page51) formal version released. may 2002 0.98 tab pin arrangement direction changed from polymide side to copper side. (page1 & page 49) the absolute maximum rating of v0 changed from 12v to 11.5v.(page35) ac timing of t cclw , t cchw, t ewhw & t ewlw changed from 60ns, 60ns, 60ns, 60ns to 90ns, 120ns, 90ns, 120ns (page37 & page 38) adding a pull-up resistor for the /reset pin.(page 42) apr. 2002 0.97 v dd2 operating voltage changed (page 36) oct. 2001 0.96 value of external capacitor changed (page 21) figure 5 changed (page 14) sep. 2001 0.95 command description addition (page 33 - 35) absolute maximum rating changed (page 36) aug. 2001 0.94 chip outline dimensions changed (page 46) pad description changed (page 4, page 8) jul. 2001 0.92 tab information addition (page 1, page47 - 50) ordering information addition (page 51) apr. 2001 0.91 divided the power input pad and power output pad (page 4) pad description changed (page 8) jan. 2001 0.9 table 10 changed (page 18) pad description changed (page 4) oct. 2000 0.8 pad location addition mar. 2000 0.0 original sep. 1999

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